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4912C–AUTO–10/06

ATA6827 [Preliminary]

3.2

Power-supply Fail

In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set

and all outputs are disabled. To detect an undervoltage, its duration has to be longer than the

undervoltage detection delay time t

age recovers to a normal operating value. The PSF bit stays high until it is reset by the SRR

(Status Register Reset) bit in the input register.

3.3

Open-load Detection

If the current through a high-side or low-side switch in the ON-state stays below the open-load

detection threshold, the open-load detection bit (OPL) in the output register is set.

The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an open

load, its duration has to be longer than the open-load detection delay time t

3.4

Overtemperature Protection

If the junction temperature of one or more output stages exceeds the thermal prewarning thresh-

old, T

temperature falls below the thermal prewarning threshold, T

bit can be read without transferring a complete 16-bit data word. The status of TP is available at

pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set

high and the data transfer is interrupted without affecting the status of input and output registers.

If the junction temperature of one or more output stages exceeds the thermal shutdown thresh-

old, T

low. The outputs can be enabled again when the temperature falls below the thermal shutdown

threshold, T

warning and shutdown threshold avoids oscillations.

3.5

Short-circuit Protection

The output currents are limited by a current regulator. Overcurrent detection is activated by writ-

ing a high to the OCS (Overcurrent Shutdown) bit in the input register. When the current in an

output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off after a

delay time (t

the output register is set to low. For OCS = low the overcurrent shutdown is inactive. The SCD

bit is also set if the current exceeds the overcurrent limitation and shutdown threshold, but the

outputs are not affected. By writing a high to the SRR bit in the input register the SCD bit is reset

and the disabled outputs are enabled.

3.6

Inhibit

Applying 0V to pin 8 (INH) inhibits the ATA6827.

All output switches are then turned off and switched to tri-state. The data in the output register is

deleted. The output switches can be activated again by switching pin 8 (INH) to 5V which ini-

tiates an internal power-on reset.