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KF2 bảng dữ liệu(PDF) 24 Page - List of Unclassifed Manufacturers |
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KF2 bảng dữ liệu(HTML) 24 Page - List of Unclassifed Manufacturers |
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24 / 29 page ![]() ©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) A/D Converter Characteristics (TA = -40 to +85 °C,1.8 V ≤ VDD = EVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD = EVDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 10 bit 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR 2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR Overall error Note1,2 AINL AVREF < 2.7 V T.B.D. %FSR 4.0 V ≤ AVREF ≤ 5.5 V 6.6 30 µs 2.7 V ≤ AVREF ≤ 5.5 V 6.6 30 µs Conversion time tCONV AVREF < 2.7 V 11 T.B.D. µs 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR 2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR Zero-scale error Note1,2 EZS AVREF < 2.7 V T.B.D. %FSR 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR 2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR Full-scale error Note1,2 EFS AVREF <2.7 V T.B.D. %FSR 4.0 V ≤ AVREF ≤ 5.5 V ±2.5 LSB 2.7 V ≤ AVREF ≤ 5.5 V ±4.5 LSB Integral linearity error Note1 ILE AVREF < 2.7 V T.B.D. LSB 4.0 V ≤ AVREF ≤ 5.5 V ±1.5 LSB 2.7 V ≤ AVREF ≤ 5.5 V ±2.0 LSB Differential linearity error Note1 DLE AVREF < 2.7 V T.B.D. %FSR Analog input voltage VAIN AVSS AVREF V Notes 1. Excludes quantization error ( ±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. POC Circuit Characteristics (TA = -40 to +85 °C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage VPOC 1.3 1.5 1.7 V Power supply rise time tPTH VDD : VPOC →1.8 V (MIN. value of VDD) 75 T.B.D mV/ms Minimum pulse width tPW T.B.D. 50 µs Notes 1. When voltage rises, time required from detection to reset release 2. When voltage drops, time required from detection to reset occur. POC Circuit Timing Supply voltage (VDD) Time Detection voltage (MIN.) Detection voltage (TYP.) Detection voltage (MAX.) tPTH tPTHD tPW tPD |
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