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KF2 bảng dữ liệu(PDF) 19 Page - List of Unclassifed Manufacturers

tên linh kiện KF2
Giải thích chi tiết về linh kiện  8-BIT SINGLE-CHIP MICROCONTROLLER
PDF  29 Pages
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nhà sản xuất  ETC [List of Unclassifed Manufacturers]
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KF2 bảng dữ liệu(HTML) 19 Page - List of Unclassifed Manufacturers

Back Button KF2 Datasheet HTML 15Page - List of Unclassifed Manufacturers KF2 Datasheet HTML 16Page - List of Unclassifed Manufacturers KF2 Datasheet HTML 17Page - List of Unclassifed Manufacturers KF2 Datasheet HTML 18Page - List of Unclassifed Manufacturers KF2 Datasheet HTML 19Page - List of Unclassifed Manufacturers KF2 Datasheet HTML 20Page - List of Unclassifed Manufacturers KF2 Datasheet HTML 21Page - List of Unclassifed Manufacturers KF2 Datasheet HTML 22Page - List of Unclassifed Manufacturers KF2 Datasheet HTML 23Page - List of Unclassifed Manufacturers Next Button
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©NEC Electronics Corporation 2004
78K0/KF2
ZUD-CC-04-0129-E
Data Published Oct 2004 N CP(K)
(2) Serial interface
(TA = -40 to +85
°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD= EVDD, VSS = EVSS = AVSS = 0 V)
(a)UART mode (UART6, dedicated baud rate generator output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Transfer rate
312.5
kbps
(b) UART mode (UART0, dedicated baud rate generator output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Transfer rate
312.5
kbps
(c) IIC0 mode
Normal mode
High speed mode
Parameter
Symbol
MIN.
. MAX
MIN.
. MAX
Unit
SCL0 clock frequency
fCLK
0
100
0
400
kHz
Start/restart condition setup time
Note1
tSU: STA
4.8
-
0.7
-
µs
hold time
tHD: STA
4.1
-
0.7
-
µs
Hold time in SCL = ”L”
tLOW
5.0
-
1.25
-
µs
Hold time in SCL = ”H”
tHIGH
5.0
-
1.25
-
µs
Data setup time (reception)
tSU: DAT
0
-
0
-
µs
Data hold time (sending)
Note2
tHD: DAT
0.47
4.0
0.23
1.00
µs
Notes 1.
The first clock pulse is generated after this period in the case of the start/restart condition.
2.
The MAX of tHD:DAT is normal transition value. Wait is occurred in the term of
ACK(acknowledge) .
Caution
Specification at 1.8 V ≤ VDD < 2.7V is not fixed.



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