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PCD5091 bảng dữ liệu(PDF) 9 Page - NXP Semiconductors

tên linh kiện PCD5091
Giải thích chi tiết về linh kiện  DECT baseband controller
PDF  16 Pages
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nhà sản xuất  PHILIPS [NXP Semiconductors]
Trang chủ  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCD5091 bảng dữ liệu(HTML) 9 Page - NXP Semiconductors

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1997 Jul 21
9
Philips Semiconductors
Objective specification
DECT baseband controller
PCD5091
P1.5
57
55
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P1.6
58
56
I/O
off
ISI8DPES
bidirectional 80C51 port pin
P1.7
59
57
I/O
off
ISI8DPES
bidirectional 80C51 port pin
VDD3V_2
60
58
−−
supply
positive supply voltage 2 (+3 V)
BZM
61
59
O
L
ANAIOD2
negative buzzer output
BZP
62
60
O
L
ANAIOD2
positive buzzer output
VSS2
63
61
−−
supply
negative supply voltage 2
VSS3
64
62
−−
supply
negative supply voltage 3
P3.0
65
63
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.1
66
64
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.2
67
65
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.3
68
66
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.4
69
67
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.5
70
68
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.6
71
69
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.7
72
70
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.0
73
71
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.1
74
72
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.2
75
73
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
A16
76
74
O
L
ISP4DPES
address bit 16 for 128 kbytes external
program memory
VDD5V_2
77
75
−−
supply
positive supply voltage 2 for the +5 V
interface
VSS4
78
76
−−
supply
negative supply voltage 4
TST1
79
77
I
−
DIDP0PES
test input 1
TST2
80
78
I
−
DIDP0PES
test input 2
P2.3
81
79
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.4
82
80
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.5
83
81
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.6
84
82
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.7
85
83
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
PSE
86
84
O
H
ISQ2CPES
program store enable (80C51); active LOW
ALE
87
85
O
H
ISQ4CPES
address latch enable (80C51)
SYMBOL
PIN
I/O
STATE
AFTER
RESET
PIN TYPE
PIN DESCRIPTION
QFP100 LQFP100



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