W39V080FA

Publication Release Date: Dec. 13, 2005

- 31 -

Revision A5

Timing Waveforms for FWH Interface Mode, continued

11.7 FGPI Register/Product ID Readout Timing Diagram

Note: During the GPI read out mode, the DQ[4:0] will capture the states(High or Low) of the FGPI[4:0] input pins. The DQ[7:5] are reserved pins

#RESET

FWH[3:0]

Start

IDSEL

Load Address "FFBC0100(hex)" in 7 Clocks for GPI Register

& "FFBC0000(hex)/FFBC0001(hex) for Product ID

CLK

1 Clock

1 Clock

Next Sta

1 Clock

2 Clocks

1 Clock

0000b

1101b

Address

Sync

TAR

1111b

Tri-State

0000b

Data out 2 Clocks

D[7:4]

Data

0000b

0001b

/0000b

0000b

0000b

/0001b

D[3:0]

A[27:24]

A[23:20]

A[19:16]

0000b

M Size

2 Clocks

TAR

1111b

Tri-State

FWH4

11.8 Reset Timing Diagram

CLK

VDD

#RESET

FWH[3:0]

FWH4