Data Sheet

ADL5507

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 13 of 34

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CFLT

An optional capacitor connected between CFLT and VLOG (pin 5) reduces the detector ripple averaging bandwidth. It slows the response of

the output and reduces noise seen on the output.

2

VPOS

Positive DC power supply. Bypass externally with a 100 pF and a 0.1 μF low ESR capacitors near this pin to ground.

3

RFIN

RF input. Internally ac-coupled with an on-chip 25 pF series capacitor. Connect a 51 Ω shunt resistor as close as possible to this pin for a

broadband 50 Ω match.

4

COMM

Device common (Ground). Connect this pin to system ground using a low impedance path.

5

VLOG

Logarithmic output. The DC output voltage at this pin is linearly proportional to the RF signal level applied to RFIN (pin 3) in dBm. In shutdown

(ENBL = low) this interface becomes high-impedance to avoid discharge of external filter capacitors.

6

ENBL

Device enable and output response selection. Connect the ENBL pin to a logic high to enable the device and select positive output slope

mode. Float, or apply VPOS/2 to the ENBL pin to enable the device and select negative output slope mode. When it is floating, the ENBL pin

self-biases to approximately half of the voltage on VPOS (pin 2). Connect the ENBL pin to a logic low to disable the device.