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PCM3060PWR bảng dữ liệu(PDF) 27 Page - Burr-Brown (TI) |
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PCM3060PWR bảng dữ liệu(HTML) 27 Page - Burr-Brown (TI) |
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27 / 45 page ![]() www.ti.com Packet Protocol 9 SDA SCL St 1-7 8 1-8 9 1-8 9 9 Sp Slave Address ACK DATA ACK DATA ACK ACK R/W R/ :ReadOperationif1;Otherwise,WriteOperation W ACK: AcknowledgementofaByteif0,not AcknowledgementofaByteif1 DATA:8Bits(Byte) Stop Condition Start Condition T0049-06 Write Operation Transmitter M M M S M M M M Data Type St Slave Address W ACK ACK ACK ACK ACK WriteData1 WriteData2 Reg Address Sp M:MasterDeviceS:SlaveDeviceSt:StartCondition :Write ACK: AcknowledgementSp:StopCondition W R0002-04 S S S S PCM3060 SLAS533 – MARCH 2007 The PCM3060 has 7 bits for its own slave address. The first six bits (MSBs) of the slave address are factory preset to 10 0011. The next bit of the address byte is the device select bit, which can be user-defined by the ADR pin (pin 27). Two PCM3060s at maximum can be connected on the same bus at one time. Each PCM3060 responds when it receives its own slave address. A master device must control packet protocol, which consists of a start condition, slave address with read/write bit, data if write or acknowledgement if read, and stop condition. The PCM3060 supports the slave receiver function. The PCM3060 supports the receiver function. A master can write to any PCM3060 registers using single or multiple accesses. The master sends a PCM3060 slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented by 1 automatically. When the index register reaches 4Ah, the next value is 40h. When undefined registers are accessed, the PCM3060 does not send an acknowledgement. Figure 31 is a diagram of the write operation. The register address and the write data are 8-bit in MSB-first format. Figure 31. Framework for Write Operation 27 Submit Documentation Feedback |
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