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CDCL6010RGZRG4 bảng dữ liệu(PDF) 19 Page - Texas Instruments

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tên linh kiện CDCL6010RGZRG4
Giải thích chi tiết về linh kiện  1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer
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CDCL6010RGZRG4 bảng dữ liệu(HTML) 19 Page - Texas Instruments

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FREQUENCY SETTINGS FOR SOME APPLICATIONS
CDCL6010
SLLS780 – FEBRUARY 2007
Table 6. PLL Bandwidth Setting
PLL
SELBW
Bandwidth(1)
C1
R
C2
On-Chip Loop
(kHz)
[3]
[2]
[1]
[0]
(nF)
(
Ω)
(nF)
Filter ON/OFF
Notes
400
0
0
0
0
N/A
N/A
N/A
ON
Default
350
0
0
1
0
2.2
8660
0
OFF
300
0
0
1
1
3.3
7500
0
OFF
250
0
1
0
0
4.7
6200
0
OFF
200
0
1
1
0
8.2
4990
0
OFF
175
1
0
0
0
10
4300
0
OFF
150
1
0
1
0
15
3740
0
OFF
125
1
1
1
1
22
3090
0
OFF
100
1
1
1
1
33
2490
0.24
OFF
75
1
1
1
1
56
1870
0.82
OFF
50
1
1
1
1
150
1210
2.70
OFF
20
1
1
1
1
680
470
18
OFF
10
1
1
1
1
3300
220
68
OFF
(1)
Refer to Functional Block Diagram for the external low pass filter architecture.
APPLICATION
PROTOCOL
Output
Output
VCO
PLL
Ref Clock
Ref Clock
PLL
Ref Clock
Ref Clock
Clock
Divider
Freq
Divider
Divider
Max Freq
Divider
Divider
Min Freq
MHz
P0, P1
GHz
N (max f)
M (max f)
MHz
N (min f)
M (min f)
MHz
10G Ethernet
312.5
4
1.250
32
8
312.5
40
1
31.25
(XAUI)
156.25
8
1.250
32
8
312.5
40
1
31.25
78.125
16
1.250
32
8
312.5
40
1
31.25
62.5
20
1.250
32
8
312.5
40
1
31.25
1G Ethernet
250
5
1.250
40
8
250
40
1
31.25
Serial ATA
125
10
1.250
40
8
250
40
1
31.25
62.5
20
1.250
40
8
250
40
1
31.25
10X FIBRE CHANNEL
159.375
8
1.275
32
8
318.75
40
1
31.875
63.75
20
1.275
32
8
318.75
40
1
31.875
CPRI
245.76
5
1.229
40
8
245.78
40
1
30.72
122.88
10
1.229
40
8
245.78
40
1
30.72
61.44
20
1.229
40
8
245.78
40
1
30.72
30.72
40
1.229
40
8
245.78
40
1
30.72
OBSAI
153.6
8
1.229
32
8
307.2
32
1
38.4
76.8
16
1.229
32
8
307.2
32
1
38.4
PCI Express
250
5
1.250
40
8
250
40
1
31.25
Serial ATA
150
8
1.200
32
8
300
32
1
37.5
75
16
1.200
32
8
300
32
1
37.5
SONET
622.08
2
1.244
32
8
311.04
40
1
31.104
311.04
4
1.244
32
8
311.04
40
1
31.104
155.52
8
1.244
32
8
311.04
40
1
31.104
62.208
20
1.244
32
8
311.04
40
1
31.104
19
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