www.ti.com

f − Single-Sideband Frequency − Hz

G002

−160

−140

−120

−100

−80

−60

−40

−20

0

10

100

1k

100M

10k

100k

1M

10M

CDCE421

SCAS842 – APRIL 2007

For the case of CDCE421 being referenced by a clean external LVCMOS input of 33.33 MHz, Figure 9 shows

the SSB phase noise plot of the output at 400 MHz from 100 Hz to 40 MHz from carrier. See Figure 12 for test

setup.

Figure 9. Phase Noise Plot for LVDS Output at 400 MHz

Table 6. Phase Noise Parameters With LVCMOS Input of 33.33 MHz and LVDS Output at 400 MHz

Phase noise specifications under following assumptions: input frequency f = 33.33 MHz (VCO = 1, prescaler = 5, output divider =

PARAMETER

MIN

TYP

MAX

UNIT

Phase noise at 100 Hz

–99

dBc/Hz

Phase noise at 1 kHz

–107

dBc/Hz

Phase noise at 10 kHz

–115

dBc/Hz

Phase noise at 100 kHz

–119

dBc/Hz

Phase noise at 1 MHz

–128

dBc/Hz

Phase noise at 10 MHz

–144

dBc/Hz

Phase noise at 20 MHz

–145

dBc/Hz

RMS jitter integrated from 12 kHz to 20 MHz

501

fs

17

Submit Documentation Feedback