P83C524IFA datasheet(58/76 Pages) PHILIPS

58 / 76 page

1997 Dec 15

Philips Semiconductors

Product speciﬁcation

8-bit microcontrollers

P83C524; P80C528; P83C528

22 I2C CHARACTERISTICS (BIT-LEVEL)

Notes

1. At fCLK = 3.5 MHz, this evaluates to 14 × 286 ns = 4 µs, i.e. the bit-level I2C interface can respond to the I2C protocol

for fCLK ≥3.5 MHz.

2. This parameter is determined by the user software, it has to comply with the I2C specification.

3. This value gives the auto-clock pulse length which meets the I2C specification for the specified XTAL1 clock

frequency range. Alternatively, the SCL pulse may be timed by software.

4. Spikes on SDA and SCL lines with a duration of less than 4

× fCLK will be filtered out.

5. The RISE time is determined by the external bus line capacitance and pull-up resistor, it must be

≤1 µs.

6. The maximum capacitance on bus lines SDA and SCL is 400 pF.

SYMBOL

PARAMETER

INPUT

OUTPUT

I2C SPEC

UNIT

SCL timing

tHD;STA

START condition hold time

≥ 14 tCK; note 1

note 2

≥ 4.0

µs

tLOW

SCL LOW time

≥ 16 tCK

note 2

≥ 4.7

µs

tHIGH

SCL HIGH time

≥ 14 tCK; note 1

≥ 80 tCK; note 3

≥ 4.0

µs

tRC

SCL RISE time

≤ 1; note 4

note 5

≤ 1.0

µs

tFC

SCL FALL time

≤ 0.3; note 4

≤ 0.3; note 6

≤ 0.3

µs

SDA timing

tSU;DAT

data set-up time

≥ 250 ns

note 2

≥ 250

tHD;DAT

data hold time

≥ 0 ns

note 2

≥ 0ns

tSU;STA

repeated START set-up time

≥ 14 tCK; note 1

note 2

≥ 4.7

µs

tSU;STO

STOP condition set

−up time

≥ 14 tCK; note 1

note 2

≥ 4.0

µs

tBUF

bus free time

≥ 14 tCK; note 1

note 2

≥ 4.7

µs

tRD

SDA RISE time

≤ 1; note 4

note 5

≤ 1.0

µs

tFD

SDA FALL time

≤ 300 ns; note 4

≤ 0.3; note 6

≤ 0.3

µs

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