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ISL51002 bảng dữ liệu(PDF) 21 Page - Intersil Corporation |
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ISL51002 bảng dữ liệu(HTML) 21 Page - Intersil Corporation |
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21 / 32 page ![]() 21 December 22, 2006 0x56 Transition threshold, (0x0A) 7:0 PADJ Threshold Threshold of transitions visible for capturing. These are the 8 MSBs of the 10-bit threshold word used for phase quality measurements. The actual 10-bit threshold used equals the value in this register times 4. 0x57 Phase Adjust Data 3, (read only) 7:0 Reserved Reserved 0x58 Phase Adjust Data 2, (read only) 7:0 Reserved Reserved 0x59 Phase Adjust Data 1, (read only) 7:0 Reserved Reserved 0x5A Phase Adjust Data 0, (read only) 7:0 Reserved Reserved 0x60 AFE CTRL, (0x00) 0 Reserved Set to 0 1 700mV calibration 0: Normal operation 1: All three inputs connected to internal ~700mV reference voltage 2 Coast Clamp Enable 0: DC restore clamping and ABLC suspended during Coast and Macrovision (default) 1: DC restore clamping and ABLC continue during Coast 3 Reserved Set to 0 4 Blue Midscale 0: Half scale analog shift not added to Blue Channel (UV) 1: Half scale analog shift added to Blue Channel (YRGB) 5 Green Midscale 0: Half scale analog shift not added to Green Channel (UV) 1: Half scale analog shift added to Green Channel (YRGB) 6 Red Midscale 0: Half scale analog shift not added to Red Channel (UV) 1: Half scale analog shift added to Red Channel (YRGB) 7 Midscale Override 0: Midscale determined by RGB/YUV bit in User Control section – settings in 0x60[6:4] are ignored (default). 1: Midscale determined by 0x60[6:4] 0x61 ADC CTRL, (0x00) 0 Dither Enable 0: Dither disabled (default) 1: Dither enabled 1 Dither Amplitude 0: 16 LSBs (default) 1: 8 LSBs 3:2 Dither Increment 00: Every Pixel (default) 01: Every HSYNC 10 and 11: Every VSYNC 4 Dither Seed Reset Set to 1 and then to 0 to reset Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) BITS FUNCTION NAME DESCRIPTION ISL51002 |
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