COM20019IP datasheet(17/81 Pages) SMSC

tên linh kiện	COM20019IP

Giải thích chi tiết về linh kiện	Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM

PDF	81 Pages

Scroll/Zoom	100%

nhà sản xuất	SMSC [SMSC Corporation]

Trang chủ	http://www.smsc.com

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17 / 81 page

DISCONTINUED DATASHEET

Diagnostic register and generates the starting

pulse of the RAM Arbitration. Typical delay time

between nRD and nRD1 is around 15nS and

between nRD1 and nRD2 is around 10nS.

Longer pulse widths are needed due to these

delays on nRD signal. However, the CPU can

insert some wait cycles to extend the width

without any impact on performance.

The RBUSTMG bit was added to Disable/Enable

the High Speed CPU Read function. It is defined

as:

RBUSTMG=0,

Disabled

(Default);

RBUSTMG=1, Enabled.

In the MOTOROLA CPU mode (DIR, nDS

mode), the same modifications apply.

RBUSTMG BIT

BUS TIMING MODE

Normal Speed CPU Read and Write

High Speed CPU Read and Normal Speed CPU Write

TRANSMISSION MEDIA INTERFACE

The bottom halves of Figures 2 and 3 illustrate the

COM20019 interface to the transmission media

used to connect the node to the network. Table 1

lists different types of cable which are suitable for

ARCNET applications.

The user may interface to the cable of choice in

one of three ways:

1 Please refer to TN7-5 – Cabling Guidelines for

the COM20020 ULANC, available from SMSC, for

recommended cabling distance, termination, and

node count for ARCNET nodes.

COM20019IP bảng dữ liệu(PDF) 17 Page - SMSC Corporation