In interrupt mode (TM=1), the ALERT pin will be activated when the temperature measurement result equals or

exceeds THIGH continuously for a number of times to the value defined by F1/F0 (as shown in Table 4). The ALERT

pin remains active until it is cleared by one of three events: a read of any register, a successful SMBus alert response,

or a shutdown command. After the ALERT pin is cleared, the device starts to compare temperature readings with the

TLOW. The ALERT pin becomes active again only when the temperature drops below TLOW for a consecutive number

of conversions as set by F1/F0 bits. The ALERT pin remains active until cleared by any of the same three clearing

events. The user can also reset the TMP112B to clear the ALERT pin state by using the global response reset

command (General Call). This operation also resets other internal registers in the TMP112B and returns

the device to compare mode (TM=0). Table 4 shows the specific configuration of the F1/F0 bits.

Table 4. Number of Over-Temperature Required to Activate the ALERT Pin

F1

F0

REQUIRED NUMBER (TIMES)

0

0

1 (Default)

0

1

2

1

0

4

1

1

6

The polarity bit (POL) in the configuration register allows the user to adjust the polarity of the ALERT pin output.

If the POL bit is set to 0 (default), the ALERT pin becomes active low. When POL bit is set to 1, the ALERT pin

becomes active high. The above situations are shown in Figure 4.

Serial Interface

Bus Overview

The TMP112B is compatible with SMBus and I2C interfaces. In the SUMBus protocol, the device that

initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be

controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the

START and STOP conditions. To address a specific device, a START condition is initiated, indicated by pulling the

data line (SDA) from a high- to low-logic level when the SCL pin is high. All slaves on the bus receive the 8-bits slave

address on the rising edge of the clock, and the last bit indicates whether a read or write operation is intended. During

the ninth clock pulse,

the addressed slave generates an acknowledge and pulls the SDA pin low to respond to the master. A data transfer

is then initiated and sent over eight clock pulses followed by an acknowledge bit. When all data are transferred, the

master generate a STOP signal to end the communication by pulling SDA from low to high when SCL is high.

During the data transfer, the SDA pin must remain stable when the SCL pin is high because any change in the

SDA pin when the SCL pin is high is interpreted as a START or STOP signal.

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