LAN91C100FD datasheet(37/67 Pages) SMSC

37 / 67 page

SMSC DS – LAN91C100FD REV. B

Page 37

Rev. 01-20-06

TYPICAL FLOW OF EVENTS FOR TRANSMIT

S/W DRIVER

MAC SIDE

ISSUE ALLOCATE MEMORY FOR TX - N

BYTES - the MMU attempts to allocate N bytes

of RAM.

WAIT

FOR

SUCCESSFUL

COMPLETION

CODE - Poll until the ALLOC INT bit is set or

enable its mask bit and wait for the interrupt.

The TX packet number is now at the Allocation

Result Register.

LOAD TRANSMIT DATA - Copy the TX packet

number into the Packet Number Register. Write

the Pointer Register, then use a block move

operation from the upper layer transmit queue

into the Data Register.

ISSUE "ENQUEUE PACKET NUMBER TO TX

FIFO" - This command writes the number

present in the Packet Number Register into the

TX FIFO. The transmission is now enqueued.

No further CPU intervention is needed until a

transmit interrupt is generated.

The enqueued packet will be transferred to the

MAC block as a function of TXENA (nTCR) bit

and of the deferral process (1/2 duplex mode

only) state.

Upon transmit completion the first word in

memory is written with the status word. The

packet number is moved from the TX FIFO into

the TX completion FIFO. Interrupt is generated

by the TX completion FIFO being not empty.

SERVICE INTERRUPT - Read Interrupt Status

Done Packet Number from the Fifo Ports

Packet Number Register.

The corresponding

status word is now readable from memory.

status word shows successful transmission,

issue RELEASE packet number command to

free up the memory used by this packet.

Remove packet number from completion FIFO

by writing TX INT Acknowledge Register.

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