LAN91C100FD datasheet(18/67 Pages) SMSC

18 / 67 page

SMSC DS – LAN91C100FD REV. B

Page 18

Rev. 01-20-06

HASH VALUE - Provides the hash value used to index the Multicast Registers. Can be used by receive routines to speed

up the group address search. The hash value consists of the six most significant bits of the CRC calculated on the

Destination Address, and maps into the 64 bit multicast table. Bits 5,4,3 of the hash value select a byte of the multicast

table,

while

bits

2,1,0

determine

the

bit

within

the

byte

selected.

Examples

the

address

mapping:

ADDRESS

HASH VALUE 5-0

MULTICAST TABLE BIT

ED 00 00 00 00 00

0D 00 00 00 00 00

01 00 00 00 00 00

2F 00 00 00 00 00

000 000

010 000

100 111

111 111

MT-0 bit 0

MT-2 bit 0

MT-4 bit 7

MT-7 bit 7

MULTCAST - Receive frame was multicast. If hash value corresponds to a multicast table bit that is set, and the address

was a multicast, the packet will pass address filtering regardless of other filtering criteria.

I/O SPACE

The base I/O space is determined by the IOS0-IOS2 inputs and the EEPROM contents. To limit the I/O space

requirements to 16 locations, the registers are assigned to different banks. The last word of the I/O area is shared by all

banks and can be used to change the bank in use. Registers are described using the following convention:

OFFSET

NAME

TYPE

SYMBOL

HIGH

BYTE

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

LOW

BYTE

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

OFFSET - Defines the address offset within the IOBASE where the register can be accessed at, provided the bank select

has the appropriate value.

The offset specifies the address of the even byte (bits 0-7) or the address of the complete word.

The odd byte can be accessed using address (offset + 1).

Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that

case the offset of each one is independently specified.

Regardless of the functional description, all registers can be accessed as doublewords, words or bytes.

The default bit values upon hard reset are highlighted below each register.

Table 2 - Internal I/O Space Mapping

BANK0

BANK1

BANK2

BANK3

TCR

CONFIG

MMU COMMAND

MT0-1

EPH STATUS

BASE

PNR

MT2-3

RCR

IA0-1

FIFO PORTS

MT4-5

COUNTER

IA2-3

POINTER

MT6-7

MIR

IA4-5

DATA

MGMT

MCR

GENERAL

DATA

REVISION

RESERVED (0)

CONTROL

INTERRUPT

ERCV

BANK SELECT

A special BANK (BANK7) exists to support the addition of external registers.

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