LAN91C96IQFP datasheet(4/109 Pages) SMSC

4 / 109 page

Non-PCI Single-Chip Full Duplex Ethernet Controller

Rev. 03-28-07

Page 4

SMSC DS – LAN91C96I

DATASHEET

Chapter 13

Package Outlines........................................................................................................... 108

List of Figures

Figure 3.1 – Pin Configuration of LAN91C96I QFP........................................................................................................9

Figure 3.2

− Pin Configuration of LAN91C96I TQFP....................................................................................................10

Figure 3.3 – System Diagram for Local Bus with Boot Prom .......................................................................................11

Figure 4.1 - LAN91C96I Internal Block Diagram ..........................................................................................................18

Figure 5.1 – Mapping and Paging vs. Receive and Transmit Area ..............................................................................21

Figure 5.2 – Transmit Queues and Mapping ................................................................................................................22

Figure 5.3 – Receive Queues and Mapping .................................................................................................................23

Figure 5.4 – LAN91C96i Internal Block Diagram with Data Path .................................................................................24

Figure 5.5 – Logical Address Generation and Relevant Registers...............................................................................25

Figure 6.1 – Data Packet Format .................................................................................................................................29

Figure 7.1 - LAN91C96I Registers ...............................................................................................................................32

Figure 7.2 – Interrupt Structure ....................................................................................................................................54

Figure 8.1 – Interrupt Service Routine .........................................................................................................................63

Figure 8.2 – RX INTR...................................................................................................................................................64

Figure 8.3 – TX INTR ...................................................................................................................................................65

Figure 8.4 – TXEMPTY INTR.......................................................................................................................................66

Figure 8.5 – Driver Send and Allocate Routines ..........................................................................................................67

Figure 8.6 – Interrupt Generation for Transmit; Receive, MMU ...................................................................................71

Figure 9.1 - MMU Packet Number Flow and Relevant Registers .................................................................................76

Figure 10.1 - 64 X 16 Serial EEPROM Map .................................................................................................................83

Figure 12.1 – Local Bus Consecutive Read Cycles.......................................................................................................91

Figure 12.2 – Local Bus Consecutive Write Cycles .......................................................................................................92

FIgure 12.3 – Local Bus Consecutive Read and Write Cycles.......................................................................................93

Figure 12.4 – Data Register Special Read Access ......................................................................................................94

Figure 12.5 – Data Register Special Write Access.......................................................................................................95

Figure 12.6 - 8-Bit Mode Register Cycles ....................................................................................................................96

Figure 12.7 – External ROM Read Access ..................................................................................................................97

Figure 12.8 – Local Bus Register Access When Using Bale .........................................................................................98

Figure 12.9 – External ROM Read Access Using Bale ................................................................................................99

Figure 12.10 - EEPROM Read...................................................................................................................................100

Figure 12.11 - EEPROM Write ...................................................................................................................................101

Figure 12.12 – External ENDEC Interface – Start of Transmit ...................................................................................102

Figure 12.13 – External ENDEC Interface – Receive Data ........................................................................................102

Figure 12.14 – Differential Output Signal Timing (10BASE-T and AUI) .....................................................................103

Figure 12.15 – Receive Timing – Start of Frame (AUI and 10BASE-T) .....................................................................104

Figure 12.16 – Receive Timing – End of Frame (AUI and 10BASE-T).......................................................................105

Figure 12.17 – Transmit Timing – End of Frame (AUI and 10BASE-T)......................................................................105

Figure 12.18 – Collision Timing (AUI) ........................................................................................................................106

Figure 12.19 – Memory Read Timing.........................................................................................................................106

Figure 12.20 – Input Clock Timing .............................................................................................................................107

Figure 12.21 – Memory Write Timing .........................................................................................................................107

Figure 13.1 - 100 Pin QFP Package Outline ..............................................................................................................108

Figure 13.2 - 100 Pin TQFP Package Outline ............................................................................................................109

List of Tables

Table 5.1 - LAN91C96I Address Space .......................................................................................................................26

Table 5.2 - Bus Transactions In Local Bus Mode .........................................................................................................26

Table 5.3 – Interrupt Merging .......................................................................................................................................26

Table 5.4 – Reset Logic ...............................................................................................................................................27

Table 5.5 - Local Bus Mode Defined States (Refer To Table 5.6 For Next States To Wake-Up Events)......................28

Table 5.6 - Local Bus Mode .........................................................................................................................................28

Table 7.1 - Transmit Loop ............................................................................................................................................36

Table 13.1 - 100 Pin QFP Package Parameters ........................................................................................................108

Table 13.2 - 100 Pin TQFP Package Parameters ......................................................................................................109

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