LAN91C96-MS datasheet(83/125 Pages) SMSC

83 / 125 page

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet

SMSC DS – LAN91C965v&3v

Page 83

Rev. 03-28-07

DATASHEET

The receive packet FIFO stores the packet numbers already received into memory, in the order they were

received. The FIFO is advanced (written) by the DMA block upon reception of a complete valid packet into

memory. The number is determined the moment the DMA block first requests memory from the MMU for

that packet. The first receive packet number in the FIFO can be read via the FIFO Ports Register, and the

data associated with it can be accessed through the receive area. The packet number can be removed

from the FIFO with or without an automatic release of its associated memory.

The FIFO is read out upon CPU command (remove packet from top of RX FIFO, or remove and release

command) after processing the receive packet in the receive area.

The width of each FIFO is 5 bits per packet number. The depth of each FIFO equals the number of

packets the LAN91C96 can handle (18).

The guideline is software transparency; the software driver should not be aware of different devices or

FIFO depths.

If the MMU memory allocation succeeded, there will be room in the transmit FIFO for

enqueuing the packet. Conversely if there is free memory for receive, there should be room in the receive

FIFO for storing the packet number.

Note that the CPU can enqueue a transmit command with a packet number that does not follow the

sequence in which the MMU assigned packet numbers. For example, when a transmission failed and it is

retried in software, or when a receive packet is modified and sent back to the network.

LAN91C96-MS bảng dữ liệu(PDF) 83 Page - SMSC Corporation