LAN91C96-MS datasheet(49/125 Pages) SMSC

49 / 125 page

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet

SMSC LAN91C965v&3v

Page 49

Rev. 03-28-07

DATASHEET

DIS LINK - This bit is used to disable the 10BASE-T link test functions. When this bit is high the

LAN91C96 disables link test functions by not generating nor monitoring the network for link

pulses. In this mode the LAN91C96 will transmit packets regardless of the link test, the EPHSR

LINK_OK bit will be set and the LINK LED will stay on. When low the link test functions are

enabled. If the link status indicates FAIL, the EPHSR LINK_OK bit will be low, while transmit

packets enqueued will be processed by the LAN91C96, transmit data will not be sent out to the

cable.

INT SEL1-0 - In LOCAL BUS mode, used to select one out of four interrupt pins. The three

unused interrupts are tristated.

INT SEL1

INT SEL0

INTERRUPT PIN USED

INTR0

INTR1

INTR2

INTR3

I/O SPACE - BANK1

OFFSET

NAME

TYPE

SYMBOL

BASE ADDRESS REGISTER

READ/WRITE

BAR

For LOCAL BUS mode only, this register holds the I/O address decode option chosen for the I/O and ROM

space. It is part of the EEPROM saved setup, and is not usually modified during run-time.

A15

A14

A13

ROM SIZE

RA18

RA17

RA16

RA15

RA14

A15 - A13 and A9 - A5 - These bits are compared in LOCAL BUS mode against the I/O address on the

bus to determine the IOBASE for LAN91C96 registers. The 64k I/O space is fully decoded by the

LAN91C96 down to a 16 location space, therefore the unspecified address lines A4, A10, A11 and A12

must be all zeros.

ROM SIZE - Determines the ROM decode area in LOCAL BUS mode memory space as follows:

00 = ROM disable

01 = 16k: RA14-18 define ROM select.

10 = 32k: RA15-18 define ROM select.

11 = 64k: RA16-18 define ROM select.

RA18-RA14 - These bits are compared in LOCAL BUS mode against the memory address on the bus to

determine if the ROM is being accessed, as a function of the ROM SIZE. ROM accesses are read only

memory accesses defined by MEMRD* going low.

For a full decode of the address space unspecified upper address lines have to be: A19 = "1", A20-A23

lines are not directly decoded, however LOCAL BUS systems will only activate SMEMRD* only when A20-

A23=0.

All bits in this register are loaded from the serial EEPROM in LOCAL BUS Mode only. In PCMCIA mode,

the I/O base is set to the default value (as in LOCAL BUS mode) as defined below.

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