2

SY89823L

Micrel, Inc.

M9999-011907

hbwhelp@micrel.com or (408) 955-1690

PACKAGE/ORDERING INFORMATION

VCCO

NC

NC

VCCI

HSTL_CLK

/HSTL_CLK

CLK_SEL

LVPECL_CLK

/LVPECL_CLK

GND

OE

NC

NC

/Q21

Q21

VCCO

VCCO

Q7

/Q7

Q8

/Q8

Q9

/Q9

Q10

/Q10

Q11

/Q11

Q12

/Q12

Q13

/Q13

VCCO

64

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64-Pin EPAD-TQFP (H64-1)

PIN DESCRIPTION

Pin Number

Pin Name

Type

Pin Function

5, 6

HSTL_CLK,

HSTL

Differential clock input selected by CLK_SEL. Can be left floating if not

/HSTL_CLK

Input

selected. Floating input, if selected, produces an indeterminate output. HSTL

input signal requires external termination 50

Ω to GND.

8, 9

LVPECL_CLK,

LVPECL

Differential clock input selected by CLK_SEL. Can be left floating. Floating

/LVPECL_CLK

Input

input, if selected, produces a LOW at the output. Requires external

termination. 75k

Ω pull-up.

7

CLK_SEL

LVTTL

Selects HSTL_CLK input when LOW and LVPECL_CLK output when HIGH.

Input

11k

Ω pull-up. Default condition selects LVPECL_CLK if left open.

11

OE

LVTTL

Enable input synchronized internally to prevent glitching of the Q0-Q21 and

Input

/Q0–/Q21 outputs. Must be a minimum of three clock periods wide if

synchronous with the CLK inputs and must meet the t

(refer to “AC Electrical Characteristics” section ). If asynchronous, must be a

minimum of four clock periods wide. 11k

Ω pull-up.

63, 61, 59, 57, 55,

Q0–Q21

HSTL

Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and

53, 51, 47, 45, 43,

Output

LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated

41, 39, 37, 35, 31,

with 50

Ω to GND. Q0–Q21 outputs are static LOW when OE = LOW.

29, 27, 25, 23, 21,

Unused output pairs may be left floating.

19, 15

62, 60, 58, 56, 54,

/Q0–/Q21

HSTL

Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and

52, 50, 46, 44, 42,

Output

LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated

40, 38, 36, 34, 30,

with 50

Ω to GND. /Q0–/Q21 outputs are static HIGH when OE = LOW.

28, 26, 24, 22, 20,

Unused output pairs may be left floating.

18, 14

4

VCCI

VCC Core

Core V

Power

0.01

µF low ESR capacitors as close to V

1, 16, 17, 32,

VCCO

VCC Output

Output Buffer V

33, 48, 49, 64

Power

with 0.01

µF low ESR capacitors as close to V

pins should be connected together on the PCB.

10

GND,

Ground pin and exposed pad must be connected to the same ground plane.

Exposed Pad

2, 3, 12, 13

NC

No Connect.

Package

Operating

Package

Lead

Part Number

Type

Range

Marking

Finish

SY89823LHC

H64-1

Commercial

SY89823LHC

Sn-Pb

H64-1

Commercial

SY89823LHC

Sn-Pb

H64-1

Commercial

SY89823LHZ with

Pb-Free

Pb-Free bar-line indicator Matte-Sn

H64-1

Commercial

SY89823LHZ with

Pb-Free

Pb-Free bar-line indicator Matte-Sn

Notes:

1. Contact factory for die availability. Dice are guaranteed at T

2. Tape and Reel.

3. Pb-Free package recommended for new designs.