ATAM510 datasheet(21/72 Pages) ATMEL

21 / 72 page

4711B–4BMCU–01/05

ATAM510

2.7.6

Clock Monitor Mode

Figure 2-15. Clock Monitoring

For trimming purposes, the ATAM510 can be put into a clock monitor mode. By forcing the test

input (TE) high, the SYSCL clock will appear on BP11 (Port 1, bit 1) and SUBCL clock on Port

BP10 (Port 1, bit 0). On releasing the TE pin, the BP10 and BP11 will resume their normal func-

tion (see Figure 2-15).

Peripheral Modules

3.1

Addressing Peripherals

Accessing the peripheral modules takes place via the I/O bus (see Figure 3-1 on page 22). The

IN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual register address-

ing scheme has been adopted which addresses the “primary register” directly. To address the

“auxiliary register”, the access must be switched with an “auxiliary switching module”. Thus, a

single IN (or OUT) to the module address will read (or write) into the module primary register.

Accessing the auxiliary register is performed with the same instruction preceded by writing the

module address into the auxiliary switching module. Byte-wide registers are accessed by multi-

ple IN (or OUT) instructions. Extended addressing is used for more complex peripheral modules,

with a larger number of registers. In this case, a bank of up to 16 subport registers are indirectly

addressed with the subport address being initially written into the auxiliary register. Please refer

to the “HARDC510.SCR” hardware interface file as a programming guideline.

SYSCL clocks

NRST

BP11

Oscillator supervisory mode

Normal operation

BP10

SUBCL clocks

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