SY10E196 datasheet(9/10 Pages) MICREL

tên linh kiện	SY10E196

Giải thích chi tiết về linh kiện	PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT

PDF	10 Pages

Scroll/Zoom	100%

nhà sản xuất	MICREL [Micrel Semiconductor]

Trang chủ	http://www.micrel.com

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9 / 10 page

Precision Edge®

SY10E196

SY100E196

Micrel, Inc.

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

delays (1111111 on the A0–A6 address bus), D7 will be

asserted to signal the need to cascade the delay to the

next E196 device. When D7 is asserted, the SET MIN

pin of chip #2 will be de-asserted and the delay will be

controlled by the A0–A6 address bus. Chip #1, on the

other hand, will have its SET MAX pin asserted, resulting

in the device delay to be independent of the A0–A6

address bus.

When the SET MAX pin of chip #1 is asserted, the D0

and D1 latches will be reset, while the rest of the latches

will be set.

In addition, to maintain monotonicity, an

additional gate delay is selected in the cascade circuitry.

As a result, when D7 of chip #1 is asserted, the delay

increases from 31.75 gates to 32 gates. A 32-gate delay

is the maximum delay setting for the E196.

When cascading multiple PDCs, it will prove more cost-

effective to use a single E196 for the MSB of the chain,

while using E195 for the lower order bits. This is due to

the fact that only one fine tune input is needed to further

reduce the delay step resolution.

SY10E196 bảng dữ liệu(PDF) 9 Page - Micrel Semiconductor