AT80C51RB2-SLSCM datasheet(24/83 Pages) ATMEL

24 / 83 page

AT80C51RD2/AT83C51Rx2

4113B–8051–03/05

Table 11. CMOD Register

CMOD - PCA Counter Mode Register (D9h)

Reset Value = 00XX X000b

Not bit addressable

The CMOD register includes three additional bits associated with the PCA (see

Figure 11 and Table 11).

•

The CIDL bit which allows the PCA to stop during idle mode.

•

The WDTE bit which enables or disables the watchdog function on module 4.

•

The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in

the CCON SFR) to be set when the PCA timer overflows.

The CCON register contains the run control bit for the PCA and the flags for the PCA

timer (CF) and each module (see Table 12).

•

Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by

clearing this bit.

•

Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an

interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can

only be cleared by software.

•

Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,

etc.) and are set by hardware when either a match or a capture occurs. These flags

can only be cleared by software.

765

43210

CIDL

WDTE

CPS1

CPS0

ECF

Bit

Number

Bit

Mnemonic

Description

7CIDL

Counter Idle Control

Cleared to program the PCA Counter to continue functioning during idle Mode.

Set to program PCA to be gated off during idle.

6WDTE

Watchdog Timer Enable

Cleared to disable Watchdog Timer function on PCA Module 4.

Set to enable Watchdog Timer function on PCA Module 4.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2CPS1

PCA Count Pulse Select

CPS1

CPS0 Selected PCA input

Internal clock f

CLK PERIPH/6

Internal clock f

CLK PERIPH/2

Timer 0 Overflow

External clock at ECI/P1.2 pin (max rate = f

CLK PERIPH/4)

1CPS0

0ECF

PCA Enable Counter Overflow Interrupt

Cleared to disable CF bit in CCON to inhibit an interrupt.

Set to enable CF bit in CCON to generate an interrupt.

AT80C51RB2-SLSCM bảng dữ liệu(PDF) 24 Page - ATMEL Corporation

AT80C51RB2-SLSCM bảng dữ liệu(HTML) 24 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

bảng dữ liệu tải về

Link URL