AT80C51RB2-SLSCM datasheet(9/83 Pages) ATMEL

9 / 83 page

AT80C51RD2/AT83C51Rx2

4113B–8051–03/05

Enhanced Features

In comparison to the original 80C52, the microcontrollers implement the following new

features:

•

X2 option

•

Dual Data Pointer

•

Extended RAM

•

Programmable Counter Array (PCA)

•

Hardware Watchdog

•

4-level Interrupt Priority System

•

Power-off Flag

•

Power On Reset

•

ONCE mode

•

ALE disabling

•

Some enhanced features are also located in the UART and the Timer 2

X2 Feature and OSC

Clock Generation

The microcontroller core needs only 6 clock periods per machine cycle. This feature

called ”X2” provides the following advantages:

•

Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

•

Saves power consumption while keeping same CPU power (oscillator power

saving).

•

Saves power consumption by dividing dynamically the operating frequency by 2 in

operating and idle modes.

•

Increases CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by software.

Description

The clock for the whole circuit and peripherals is first divided by two before being used

by the CPU core and the peripherals.

This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is

bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.

Figure 2 shows the clock generation block diagram. X2 bit is validated on the rising edge

of the XTAL1

÷ 2 to avoid glitches when switching from X2 to standard mode. Figure 3

shows the switching mode waveforms.

Figure 2. Clock Generation Diagram

XTAL1

CKCON0

8-bit Prescaler

OSC

XTAL

XTAL1:2

CKRL

CLK Periph

CLK CPU

Idle

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