AT89LP2052 datasheet(49/90 Pages) ATMEL

49 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

21. Instruction Set Summary

The AT89LP2052/LP4052 is fully binary compatible with the MCS-51 instruction set. The

difference between the AT89LP2052/LP4052 and the standard 8051 is the number of cycles

required to execute an instruction. Instructions in the AT89LP2052/LP4052 may take 1, 2, 3 or 4

clock cycles to complete. The execution times of most instructions may be computed using

Table 21-1.

Table 20-2.

WDTCON – Watchdog Control Register

WDTCON Address = A7H

Reset Value = 0000 XX00B

Not Bit Addressable

PS2

PS1

PS0

WDIDLE

–

WDTOVF

WDTEN

Bit

654

321

Symbol

Function

PS2

PS1

PS0

Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal

period of 16K clock cycles. When all three bits are set to 1, the nominal period is 2048K clock cycles.

WDIDLE

Disable/enable the Watchdog Timer in IDLE mode. When WDIDLE = 0, WDT continues to count in IDLE mode. When

WDIDLE = 1, WDT freezes while the device is in IDLE mode.

WDTOVF

Watchdog Overflow Flag. Set when a WDT reset is generated by the WDT timer overflow. Also set when an incorrect

sequence is written to WDTRST. Must be cleared by software.

WDTEN

Watchdog Enable Flag. This bit is READ-ONLY and reflects the status of the WDT (whether it is running or not). The

WDT is disabled after any reset and must be re-enabled by writing 1EH/E1H to WDTRST

Table 20-3.

WDTRST – Watchdog Reset Register

WDTCON Address = A6H

(Write-Only)

Not Bit Addressable

–

–––

––

Bit

654

321

The WDT is enabled by writing the sequence 1EH/E1H to the WDTRST SFR. The current status may be checked by reading

the WDTEN bit in WDTCON. To prevent the WDT from resetting the device, the same sequence 1EH/E1H must be written to

WDTRST before the time-out interval expires.

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