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AT89LP2052 bảng dữ liệu(PDF) 45 Page - ATMEL Corporation |
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AT89LP2052 bảng dữ liệu(HTML) 45 Page - ATMEL Corporation |
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45 / 90 page ![]() 45 3547F–MICRO–6/06 AT89LP2052/LP4052 Figure 18-4. SPI Transfer Format with CPHA = 0 Note: *Not defined but normally MSB of character just received Figure 18-5. SPI Transfer Format with CPHA = 1 Note: *Not defined but normally LSB of previously transmitted character 18.4 SPI Pin Configuration Before using the Serial Peripheral Interface the four SPI pins – SCK, MISO, MOSI and SS – must be properly configured for the desired functionality. See Section 14.7 “Port Alternate Func- tions” on page 20. When the SPI is in Master mode, SCK and MOSI must be configured as bidirectional or output, with P1.7 and P1.5 set to “1”. MISO should be input-only, or bidirectional with P1.6 set to “1”. When the SPI is in Slave mode, SCK, MOSI and SS must be configured as input-only, or as bidirectional with P1.7, P1.6 and P1.4 set to “1”. MISO should be set as bidirec- tional or output, with P1.6 set to “1”. If all four pins are set as bidirectional and their respectively port bits are all “1”, it is possible to switch between Master and Slave mode without reconfiguring the pins. MSB 6 5 4 3 2 1 LSB 1 2 3 4 5 6 7 8 MSB * 65 4 3 2 1 LSB SCK CYCLE # (FOR REFERENCE) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) |
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