AT43USB325 datasheet(32/109 Pages) ATMEL

32 / 109 page

3355C–USB–4/05

AT43USB325

4.13

USB Endpoint Interrupt Sources

An assertion or activation of one or more bits in the endpoint's Control and Status Register trig-

gers the endpoint interrupts. These triggers are different for control and non-control endpoints as

described in the table below. Please refer to the Control and Status Register for more

information.

4.13.1

USB Interrupt Status Register – UISR

• Bit 7 – SOF INT: Start of Frame Interrupt

This bit is asserted after the USB hardware receives a valid SOF packet.

• Bit 6 – EOF2 INT: EOF2 Interrupt

This bit is asserted 10 clocks before the expected start of a frame.

• Bit 5 – Res: Reserved Bit

This bit is reserved and always reads as zero.

• Bit 4 – FEP3 INT: Function End-point 3 Interrupt

• Bit 3 – HEP0 INT: Hub Endpoint 0 Interrupt

• Bit 2 – FEP2 INT: Function Endpoint 2 Interrupt

• Bit 1 – FEP1 INT: Function Endpoint 1 Interrupt

• Bit 0 – FEP0 INT: Function Endpoint 0 Interrupt

The hub and function interrupt bits will be set by the hardware whenever the following bits in the

corresponding endpoint's Control and Status Register are modified by the USB hardware:

RX OUT Packet is set (control and OUT endpoints)

TX Packet Ready is cleared AND TX Complete is set (control and IN endpoints)

RX SETUP is set (control endpoints only)

TX Complete is set

Table 4-4.

USB Endpoint Interrupt Sources

Bit

Endpoint type

RX_OUT_PACKET

CONTROL, OUT

TX_COMPLETE

CONTROL, IN

STALL_SENT

CONTROL, IN

RX_SETUP

CONTROL

Bit

$1FF7

SOF INT

EOF2 INT

–

FE3 INT

HEP0 INT

FE2 INT

FE1 INT

FE0 INT

UISR

Read/Write

Initial Value

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