AT43USB325 datasheet(79/109 Pages) ATMEL

79 / 109 page

3355C–USB–4/05

AT43USB325

8.3.12

Function Endpoint 1,2,3 Service Routine Register – FCSR1,2,3

• Bit 7..4 – Reserved

These bits are reserved in the AT43USB325 and will read as zero.

• Bit 3 – STALL SENT

The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this

bit when responding to a Get Status[Endpoint] request. It is a read only bit and that is cleared

indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowledge

• Bit 2 – Reserved

This bit is reserved in the AT43USB325 and will read as zero.

• Bit 1 – RX OUT PACKET

The USB hardware sets this bit after it has stored the data of an OUT transaction in the FIFO.

While this bit is set, the hardware will NAK all OUT tokens. The USB hardware will not overwrite

the data in the FIFO except for an early set-up. RX OUT Packet is used by a BULK OUT or ISO

OUT or INT OUT endpoint.

Setting this bit causes an interrupt to the microcontroller if the interrupt is enabled. FW clears

this bit after the FIFO contents have been read by writing a one to the RX_SETUP_ACK bit of

the Control and Acknowledge Register.

• Bit 0 – TX COMPLETE: Transmit Completed

This bit is used by the endpoint hardware to signal to the microcontroller that the IN transaction

was completed successfully. This bit is read only and is cleared indirectly by writing a one to the

TX_COMPLETE_ACK bit of the Control and Acknowledge Register.

Bit

7654

Function EP1 $1FDC

––––

STALL SENT

–

RX OUT PACKET

TX COMPLETE

FCSR1

Function EP2 $1FDB

––––

STALL SENT

–

RX OUT PACKET

TX COMPLETE

FCSR2

Function EP3 $1FDA

––––

STALL SENT

–

RX OUT PACKET

TX COMPLETE

FCSR3

Read/Write

RRRR

Initial Value

0000

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