AT43USB355 datasheet(58/115 Pages) ATMEL

58 / 115 page

AT43USB355

2603G–USB–04/06

SPI Status Register – SPSR

•Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if

SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low

when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by the hard-

ware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is

cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI

Data Register (SPDR).

•Bit 6 – WCOL: Write Collision Flag

The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The

WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when

WCOL is set (one), and then accessing the SPI Data Register.

• Bit 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT43USB355 and will always read as zero.

SPI Data Register – SPDR

The SPI Data Register is a read/write register used for data transfer between the register file

and the SPI Shift register. Writing to the register initiates data transmission. Reading the regis-

ter causes the Shift Register Receive buffer to be read.

Bit

543

$0E ($2E)

SPIF

WCOL

–

SPSR

Read/Write

Initial Value

Bit

$0F ($2F)

MSB

–

LSB

SPDR

Read/Write

R/W

Initial Value

Undefined

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