LP87702 datasheet(12/99 Pages) TI

12 / 99 page

Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and

IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx =

1 V, unless otherwise noted. (1) (2)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUT SIGNALS SCL, SDA, NRST, EN1, EN2, EN3, CLKIN,

WDI

VIL

Input low level

0.4

VIH

Input high level

1.2

VHYS

Hysteresis of Schmitt

Trigger inputs

200

ENx, CLKIN, WDI pull-

down resistance

ENx_PD = 1, CLKIN_PD = 1, WDI_PD = 1

500

kΩ

NRST pull-down

resistance

Always enabled

500

kΩ

DIGITAL OUTPUT SIGNALS nINT, SDA

VOL

Output low level

SDA: ISOURCE = 20 mA

0.5

nINT: ISOURCE = 2 mA

0.4

External pull-up resistor

for nINT

To VIO Supply

kΩ

DIGITAL OUTPUT SIGNALS PGOOD, PG1, GPO0, GPO1, GPO2,

WD_RESET

VOL

Output low level

ISOURCE = 2 mA

0.4

VOH

Output high level,

configured to push-pull

ISINK = 2 mA

VVANA - 0.4

VVANA

VPU

Supply voltage for

external pull-up resistor,

configured to open-drain

VVANA

RPU

External pull-up resistor,

configured to open-drain

kΩ

ALL DIGITAL INPUTS

ILEAK

Input current

All logic inputs except NRST, over pin voltage

range, when PD not enabled

−1

µA

NRST, over pin voltage range. Other logic

inputs when PD enabled.

–1

µA

(1)

All voltage values are with respect to network ground.

(2)

Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis.

(3)

The maximum output current can be limited by the forward current limit ILIM FWD. The maximum output current is also limited by

the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction

temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.

(4)

The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current. Applies when

internal oscillator is used.

(5)

The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage and

the inductor current level.

(6)

The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.

LP87702-Q1

SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021

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