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INA700 bảng dữ liệu(PDF) 7 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  INA700 40 V, 16-Bit, I2C Output Digital Power Monitor in WCSP with 2 mΩ EZShunt™ Technology
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INA700 bảng dữ liệu(HTML) 7 Page - Texas Instruments

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6.6 Timing Requirements (I2C)
MIN
NOM
MAX
UNIT
I2C BUS (FAST MODE)
F(SCL)
I2C clock frequency
1
400
kHz
t(BUF)
Bus free time between STOP and START conditions
600
ns
t(HDSTA)
Hold time after a repeated START condition. After this period, the first
clock is generated.
100
ns
t(SUSTA)
Repeated START condition setup time
100
ns
t(SUSTO)
STOP condition setup time
100
ns
t(HDDAT)
Data hold time
10
900
ns
t(SUDAT)
Data setup time
100
ns
t(LOW)
SCL clock low period
1300
ns
t(HIGH)
SCL clock high period
600
ns
tF
Data fall time
300
ns
tF
Clock fall time
300
ns
tR
Clock rise time
300
ns
I2C BUS (HIGH-SPEED MODE)
F(SCL)
I2C clock frequency
10
2940
kHz
t(BUF)
Bus free time between STOP and START conditions
160
ns
t(HDSTA)
Hold time after a repeated START condition. After this period, the first
clock is generated.
100
ns
t(SUSTA)
Repeated START condition setup time
100
ns
t(SUSTO)
STOP condition setup time
100
ns
t(HDDAT)
Data hold time
10
125
ns
t(SUDAT)
Data setup time
20
ns
t(LOW)
SCL clock low period
200
ns
t(HIGH)
SCL clock high period
60
ns
tF
Data fall time
80
ns
tF
Clock fall time
40
ns
tR
Clock rise time
40
ns
6.7 Timing Diagram
SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
t
(BUF)
S
S
P
P
Figure 6-1. I2C Timing Diagram
www.ti.com
INA700
SBOSAB4A – MAY 2023 – REVISED SEPTEMBER 2023
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: INA700



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