WM9713LGEFLSLASHV datasheet(17/108 Pages) WOLFSON

17 / 108 page

Pre-Production

WM9713L

PP Rev 3.0 June 2006

SAMPLE RATE

VOICE DAC CLK

FREQUENCY

HIFI CLK

FREQUENCY

8ks/s voice and HIFI

2.048MHz

24.576MHz

8ks/s voice only (power save)

2.048MHz

4.096MHz

16ks/s voice and HIFI

4.096MHz

24.576MHz

16ks/s voice only (power save)

4.096MHz

8.192MHz

32ks/s voice and HIFI

8.192MHz

24.576MHz

48ks/s voice and HIFI

12.288MHz

24.576MHz

Table 3 Clock Division Mode Table

PEN ADC

The clock for the AUXADC nominally runs at 768kHz and is derived from BITCLK. The divisor for the

clock generator is set by PENDIV. This enables the AUXADC clock frequency to be set according to

power consumption and conversion rate considerations.

PLL MODE

The PLL operation is controlled by register 46h (see Table 4) and has two modes of operation:

•

Integer N

•

Fractional N

The PLL has been optimized for nominal input clock (PLL_IN) frequencies in the range 8.192MHz –

19.661MHz (LF=0) and 2.048MHz – 4.9152MHz (LF=1).

Through use of a clock divider (div by 2 / 4) on the input to the PLL frequencies up to 78.6MHz can

be accommodated. The input clock divider is enabled by DIVSEL (0=Off) and the division ratio is set

by DIVCTL (0=div2, 1=div4).

Figure 3 PLL Architecture

WM9713LGEFL/V bảng dữ liệu(PDF) 17 Page - Wolfson Microelectronics plc

WM9713LGEFL/V bảng dữ liệu(HTML) 17 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL