WM8955BLGECOSLASHV datasheet(15/44 Pages) WOLFSON

15 / 44 page

Production Data

WM8955BL

PD Rev 4.1 February 2007

INTERNAL POWER ON RESET CIRCUIT

VDD

GND

AVDD

DCVDD

DGND

Internal PORB

Power on Reset

Circuit

Figure 6 Internal Power on Reset Circuit Schematic

The WM8955BL includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used to

reset the digital logic into a default state after power up. The power on reset circuit is powered from

DCVDD and monitors DCVDD and AVDD. It asserts PORB low if DCVDD or AVDD are below a

minimum threshold.

Figure 7 Typical Power-Up Sequence

Figure 7 shows a typical power-up sequence. When DCVDD and AVDD rise above the minimum

thresholds, Vpord_dcvdd and Vpord_avdd, there is enough voltage for the circuit to guarantee the

Power on Reset is asserted low and the chip is held in reset. In this condition, all writes to the control

interface are ignored. When DCVDD rises to Vpor_dcvdd_on and AVDD rises to Vpor_avdd_on,

PORB is released high and all registers are in their default state and writes to the control interface

may take place. If DCVDD and AVDD rise at different rates then PORB will only be released when

DCVDD and AVDD have both exceeded the Vpor_dcvdd_on and Vpor_avdd_on thresholds.

On power down, PORB is asserted low whenever DCVDD drops below the minimum threshold

Vpor_dcvdd_off or AVDD drops below the minimum threshold Vpor_avdd_off.

SYMBOL

MIN

TYP

MAX

UNIT

Vpord_dcvdd

0.4

0.6

0.8

Vpor_dcvdd_on

0.9

1.26

1.6

Vpor_avdd_on

0.5

0.7

0.9

Vpor_avdd_off

0.4

0.6

0.8

Table 2 Typical POR Operation (typical values, not tested)

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