WM8772SEDSSLASHV datasheet(66/73 Pages) WOLFSON

66 / 73 page

WM8772EFT – 32 LEAD TQFP

Production Data

PD Rev 4.2 October 2005

BIT

LABEL

DEFAULT

DESCRIPTION

0001100

Interface Control

ADCBCP

ADCBCLK Polarity (DSP Modes):

0: normal BCLK polarity

1: inverted BCLK polarity

MUTE PIN DECODE

The MUTE pin can either be used an output or an input. When used as an input the MUTE pins

action can controlled by setting the DZFM bit to select the corresponding DAC for applying the MUTE

to. As an output its meaning is selected by the DZFM control bits. By default selecting the MUTE to

represent if DAC1 has received more than 1024 midrail samples will cause the MUTE to be asserted

a softmute on DAC1. Disabling the decode block will cause any logical high on the MUTE pin to

apply a softmute to all DACs.

BIT

LABEL

DEFAULT

DESCRIPTION

0001100

ADC Control

MPD

MUTE Pin Decode Disable:

0: MUTE pin decode enable

1: MUTE pin decode disable

DAC TO ADC SYNC

If the DAC and ADC use the same MCLK, and they are operating in the same fs mode setting the

SYNC bit will improve performance by synchronising the internal clock between the two blocks.

Setting this at any other time may or may not improve or degrade the performance of the device.

BIT

LABEL

DEFAULT

DESCRIPTION

0001100

SYNC Control

SYNC

SYNC Function:

0: Disable

1: Enable

WM8772SEDS/V bảng dữ liệu(PDF) 66 Page - Wolfson Microelectronics plc

WM8772SEDS/V bảng dữ liệu(HTML) 66 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

bảng dữ liệu tải về

Link URL