CC2500-RTR1 datasheet(24/84 Pages) TI

24 / 84 page

CC2500

PRELIMINARY Data Sheet (Rev.1.2)

SWRS040A

Page 24 of 83

internally according to the control coding. It is

only possible to change state with this

functionality. That means that for instance RX

will not be restarted if SI and SCLK are set to

RX and CSn toggles. When CSn is low the SI

and SCLK has normal SPI functionality.

All pin control command strobes are executed

immediately, except the SPWD strobe, which is

delayed until CSn goes high.

CSn

SCLK

Function

Chip unaffected by

SCLK

/SI

↓

Generates SPWD strobe

↓

Generates STX strobe

↓

Generates SIDLE strobe

↓

Generates SRX strobe

SPI

mode

SPI

mode

SPI mode (wakes up into

IDLE if in SLEEP/XOFF)

Table 18: Optional pin control coding

12 Data Rate Programming

The data rate used when transmitting, or the

data rate expected in receive is programmed

the

MDMCFG3.DRATE_M

and

the

MDMCFG4.DRATE_E

configuration registers.

The data rate is given by the formula below.

As the formula shows, the programmed data

rate depends on the crystal frequency.

()

XOSC

DRATE

DATA

DRATE

⋅

256

The following approach can be used to find

suitable values for a given data rate:

256

log

−

⋅

⎥

⎦

⎥

⎢

⎣

⎢

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

⋅

DRATE

XOSC

DATA

XOSC

DATA

DRATE

If DRATE_M is rounded to the nearest integer

and becomes 256, increment DRATE_E and

use DRATE_M=0.

The data rate can be set from 1.2 kbps to 500

kbps with the minimum step size of:

Data rate

start

[kbps]

Typical

data rate

[kbps]

Data rate

stop [kbps]

Data rate

step size

[kbps]

0.8

1.2/2.4

3.17

0.0062

3.17

4.8

6.35

0.0124

6.35

9.6

12.7

0.0248

12.7

19.6

25.4

0.0496

25.4

38.4

50.8

0.0992

50.8

76.8

101.6

0.1984

101.6

153.6

203.1

0.3967

203.1

250

406.3

0.7935

406.3

500

1.5869

Table 19: Data rate step size

13 Receiver Channel Filter Bandwidth

In order to meet different channel width

requirements, the receiver channel filter is

programmable. The MDMCFG4.CHANBW_E and

MDMCFG4.CHANBW_M

configuration registers

control the receiver channel filter bandwidth,

which scales with the crystal oscillator

frequency. The following formula gives the

relation between the register settings and the

channel filter bandwidth:

CHANBW

XOSC

channel

CHANBW

)·

(

⋅

The

CC2500 supports the following channel

filter bandwidths:

CC2500-RTR1 bảng dữ liệu(PDF) 24 Page - Texas Instruments

CC2500-RTR1 bảng dữ liệu(HTML) 24 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

bảng dữ liệu tải về

Link URL