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TDA7529 bảng dữ liệu(PDF) 35 Page - STMicroelectronics

tên linh kiện TDA7529
Giải thích chi tiết về linh kiện  RF front-end for AM/FM DSP car-radio with IF sampling
PDF  60 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

TDA7529 bảng dữ liệu(HTML) 35 Page - STMicroelectronics

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TDA7529
Registers description
35/60
6
Registers description
Figure 16.
Registers description
No
name
r/w
MSB (7)
6
5
4
3
2
1
LSB (0)
Power
on
default
0 Short reg
r/w
x
x
ShAGC
ShPLL
ADCen
GPIOen
PWR
00h
1 ADCctrl
r/w
ADCclk
ADCs2
ADCs1
ADCs0
RCenable
ADCautomode
Temp_pwr
00h
2 GPIOval
r/w
GPO8_AMAGCv
GPO7_FMAGCv
GPIO6_MISO
GPIO5_Aout
GPO4_AMcas
CP_curr_switch
GPIO2io
GPIO1io
00h
3 AGCmixCtrl
r/w
IFin1_AM_FM
KeyAGCen
FMAGCpwr
AMAGCpwr
MixinFMAM
BalunoutIMP
Mixout1
Mixout2
00h
4 Misc1
r/w
WAIT60ms(4)
WAIT60ms(3)
WAIT60ms(2)
WAIT60ms(1)
WAIT60ms(0)
disvcc
PLLtest
AMAGC_Isink
00h
5 DivR
r/w
divr7
divr6
divr5
divr4
divr3
divr2
divr1
divr0
00h
6 IFAGC_SH
r/w
IFAGC_FM_AM
IFAGCthr2
IFAGCthr1
IFAGCthr0
GPIO5 output
IFsection_pwr
00h
7 FMAGC
r/w
FMthr3
FMthr2
FMthr1
FMthr0
FMAGCmodeC1
FMAGCmodeC0
FMAGCmodeV1
FMAGCmodeV0
00h
8FM_AM_Vthr
r/w
AMAGCfat
AFH_MUX
Vthr5
Vthr4
Vthr3
Vthr2
Vthr1
Vthr0
00h
9 MIXalign1
r/w
IFAMP_Ictrl2
IFAMP_Ictrl1
IredH
IredL
Casc_ctrl
IMRF2
IMRF1
IMRF0
00h
10 MIXalign2
r/w
IMRph3
IMRph2
IMRph1
IMRph0
IMRG3
IMRG2
IMRG1
IMRG0
00h
11 PLLctrl
r/w
DZ4
DZ3
DZ2
DZ1
CPcur_800u
SWfref
divRen
PLLpwr
00h
12 PLLctrl2
r/w
FUNC
MODE2
MODE1
MODE0
DS4
DS3
DS2
DS1
00h
13 PLLtest
r/w
POL
PFD_D1
PFD_D0
PLLT4
PLLT3
PLLT2
PLLT1
PLLT0
00h
14 Misc2
r/w
IFAGCin4ctrl
EnSMOOTH
reg48sel
IFAMP_Ictrl0
RCfreq_1
RCfreq_0
VCOMag1
VCOMag0
00h
15 WAIT_LOCK
r/w
WAIT LOCK(4)
WAIT LOCK(3)
WAIT LOCK(2)
WAIT LOCK(1)
WAIT LOCK(0)
DIVVtest
VCOext
LOCK_bit
00h
16 AGCtc_A
r/w
IFAGCtcAM
IFAGCtcFM
AMtc1
AMtc0
FMtc3
FMtc2
FMtc1
FMtc0
00h
17 AMAGC_A
r/w
AMthr3
AMthr2
AMthr1
AMthr0
AMAGCmodeC1
AMAGCmodeC0
AMAGCmodeV1
AMAGCmodeV0
00h
18 GPIOm_A
r/w
GPO8hl
GPO7hl
GPIO6hl
GPIO5hl
GPO4hl
GPIO2hl
GPIO1hl
00h
19 IFCTRL_A
r/w
IFin0_Std_IBOC
IFAmpgainA2
IFAmpgainA1
IFAmpgainA0
MixinFM
AMAGCinbuffer
RCtest
00h
20
r/w
WAIT1ms(5)
WAIT1ms(4)
WAIT1ms(3)
WAIT1ms(2)
WAIT1ms(1)
WAIT1ms(0)
00h
21 DivN_A1
r/w
divnA20
divnA19
divnA18
divnA17
divnA16
divnA15
divnA14
divnA13
00h
22 DivN_A2
r/w
divnA12
divnA11
divnA10
divnA9
divnA8
divnA7
divnA6
divnA5
00h
23 DivN_A3
r/w
divnA4
divnA3
divnA2
divnA1
divnA0
00h
24 DivV_A
r/w
VCO1r
divVA6
divVA5
divVA4
divVA3
divVA2
divVA1
divVA0
00h
25 CPcur_A
r/w
CPAh3
CPAh2
CPAh1
CPAh0
CPAl3
CPAl2
CPAl1
CPAl0
00h
26 DAC1_A
r/w
DAC1A8
DAC1A6
DAC1A5
DAC1A4
DAC1A3
DAC1A2
DAC1A1
DAC1A1
00h
27 DAC2_A
r/w
DAC2A8
DAC2A6
DAC2A5
DAC2A4
DAC2A3
DAC2A2
DAC2A1
DAC2A1
00h
28 PLL_DAC_A
r/w
IQselA
VCOsw
DAC2A0
DAC1A0
DAC2off
DAC1off
00h
29 Misc4_A
r/w
WAIT2ms(5)
WAIT2ms(4)
WAIT2ms(3)
WAIT2ms(2)
WAIT2ms(1)
WAIT2ms(0)
MIN16
00h
30
r/w
WAIT0.5ms(5)
WAIT0.5ms(4)
WAIT0.5ms(3)
WAIT0.5ms(2)
WAIT0.5ms(1)
WAIT0.5ms(0)
AGCtest1
AGCtest0
00h
31
r/w
IF test
ADC test
ADCDAC5
ADCDAC4
ADCDAC3
ADCDAC2
ADCDAC1
ADCDAC0
00h
32 AGCtc_B
r/w
00h
33 AMAGC_B
r/w
00h
34 GPIOm_B
r/w
00h
35 IFCTRL_B
r/w
00h
36 AMFilt_B
r/w
00h
37 DivN_B1
r/w
00h
38 DivN_B2
r/w
00h
39 DivN_B3
r/w
00h
40 DivV_B
r/w
00h
41 CPcur_B
r/w
00h
42 DAC1_B
r/w
00h
43 DAC2_B
r/w
00h
44 PLL_DAC_B
r/w
00h
45 Misc4_B
r/w
00h
46
00h
47
00h
48 READ_Status
r
lock
GPIO6r
GPIO5r
MaskMetal1
MaskMetal0
MaskSet1
MaskSet0
00h
49 READ_ADC
r
ADCok
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
00h
this byte is valid on the output if bit SHAGC is set to '1', otherwise byte Nr. 16 is valid on the output
all bytes from 33 to 45 are valid on the output if SHPLL is set to '1', otherwise byte 17 to 29 are valid on the output
ADCstart



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