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ADFS7124-8BBCPZ bảng dữ liệu(PDF) 64 Page - Analog Devices

tên linh kiện ADFS7124-8BBCPZ
Giải thích chi tiết về linh kiện  8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
PDF  93 Pages
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nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
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ADFS7124-8BBCPZ bảng dữ liệu(HTML) 64 Page - Analog Devices

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Data Sheet
ADFS7124-8
DIGITAL FILTER
analog.com
Rev. 0 | 64 of 93
SINC3/SINC4
FILTER
MODULATOR
AVERAGING
BLOCK
POST
FILTER
Figure 109. Post Filters
Table 61 shows the output data rates with the accompanying
settling times and rejection.
When continuously converting on a single channel, the first conver-
sion requires a time of tSETTLE. Subsequent conversions occur at
1/fADC. When multiple channels are enabled (either manually or
using the sequencer), the settling time is required to generate a
valid conversion on each enabled channel.
Table 61. ADFS7124-8 Post Filters: Output Data Rate, Settling Time (tSETTLE), and Rejection
Output Data Rate
(SPS)
f3dB (Hz)
tSETTLE, Full Power
Mode (ms)
tSETTLE, Mid Power
Mode (ms)
tSETTLE, Low Power
Mode (ms)
Simultaneous Rejection of 50 Hz ± 1 Hz and 60 Hz ±
1 Hz (dB)1
27.27
17.28
38.498
38.998
39.662
47
25
15.12
41.831
42.331
42.995
62
20
13.38
51.831
52.331
52.995
86
16.67
12.66
61.831
62.331
62.995
92
1 Stable controllerclock used.



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