PSD835G2 datasheet(26/102 Pages) STMICROELECTRONICS

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PSD835G2

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Figure 6. Selecting the Upper or Lower Block in a Primary Flash Memory Sector

Ready/Busy (PE4)

This signal can be used to output the Ready/Busy

status of the PSD. The output on Ready/Busy

(PE4) is a ’0’ (Busy) when Flash memory blocks

are being written to, or when the Flash memory

block is being erased. The output is a '1' (Ready)

when no WRITE or Erase cycle is in progress.

Memory Operation

The primary Flash memory and secondary Flash

memory are addressed through the MCU Bus In-

terface. The MCU can access these memories in

one of two ways:

–

The MCU can execute a typical bus WRITE or

READ operation just as it would if accessing a

RAM or ROM device using standard bus

cycles.

–

The MCU can execute a specific instruction

that consists of several WRITE and READ

operations. This involves writing specific data

patterns to special addresses within the Flash

memory to invoke an embedded algorithm.

These instructions are summarized in Table

Table 28., page 27.

Typically, the MCU can read Flash memory using

READ operations, just as it would read a ROM de-

vice. However, Flash memory can only be altered

using specific Erase and Program instructions. For

example, the MCU cannot write a single byte di-

rectly to Flash memory as it would write a byte to

RAM. To program a byte into Flash memory, the

MCU must execute a Program instruction, then

test the status of the Program cycle. This status

test is achieved by a READ operation or polling

Ready/Busy (PE4).

Flash memory can also be read by using special

instructions to retrieve particular Flash device in-

formation (sector protect status and ID).

DPLD

ARRAY

FA15

FLASH MEMORY CHIP SELECT PINS FS0-FS7

PRIMARY

FLASH

MEMORY

SECTOR

A15

ADDR A15

NVM CONTROL BIT(1)

A14-A0

MUX

ai07653

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