NAND04GA3C2A datasheet(25/51 Pages) STMICROELECTRONICS

25 / 51 page

NAND04GA3C2A, NAND04GW3C2A

6 Device operations

25/51

6.10.2

P/E/R Controller and Cache Ready/Busy Bit (SR6)

Status Register bit SR6 has two different functions depending on the current operation.

During Cache Read operations SR6 acts as a Cache Ready/Busy bit, which indicates

whether the Cache Register is ready to accept new data. When SR6 is set to '0', the Cache

During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the

P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R

Controller is active (device is busy); when the bit is set to ‘1’, the P/E/R Controller is inactive

(device is ready).

6.10.3

P/E/R Controller Bit (SR5)

The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or

inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R Controller is active; when the

bit is set to ‘1’, the P/E/R Controller is inactive.

6.10.4

Error Bit (SR0)

The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The

Error Bit is set to ’1’ when a program or erase operation has failed to write the correct data to

the memory. If the Error Bit is set to ‘0’ the operation has completed successfully.

6.10.5

SR4, SR3, SR2 and SR1 are Reserved

NAND04GA3C2A bảng dữ liệu(PDF) 25 Page - STMicroelectronics