NAND04GA3C2A datasheet(11/51 Pages) STMICROELECTRONICS

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NAND04GA3C2A, NAND04GW3C2A

2 Memory array organization

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Memory array organization

The memory array is made up of NAND structures where 32 cells are connected in series.

The memory array is organized in blocks where each block contains 128 pages. The array is

split into two areas, the main area and the spare area. The main area of the array is used to

store data whereas the spare area is typically used to store software flags or Bad Block

identification.

The pages are split into a 2048 Byte main area and a spare area of 64 Bytes.Refer to

Figure 4: Memory Array Organization.

2.1

Bad blocks

The NAND04GA3C2A and NAND04GW3C2A devices may contain Bad Blocks, that is

blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional

Bad Blocks may develop during the lifetime of the device.

The Bad Block Information is written prior to shipping (refer to Section 9.1: Bad block

management for more details).

Table 4: Valid Blocks shows the minimum number of valid blocks in each device. The values

shown include both the Bad Blocks that are present when the device is shipped and the Bad

Blocks that could develop later on.

These blocks need to be managed using Bad Blocks Management and Block Replacement

(refer to Section 9: Software algorithms).

Table 4.

Valid Blocks

Density of Device

Min

Max

4 Gbits

2008

2048

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