NB650/NB650H

– 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS

NB650/NB650H Rev. 1.13

www.MonolithicPower.com

14

10/7/2019

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Preliminary Specifications Subject to Change

© 2019 MPS. All Rights Reserved.

APPLICATION INFORMATION

Setting the Output Voltage-Large ESR Caps

A resistor divider from the output voltage to the

FB pin sets the output voltage. Changing the VID

codes for the NB650/NB650H accomplishes the

same thing.

When there is no external ramp, the output

voltages are set by feedback resistors R1 and

R2A, R2B and R2C. First, choose R1 within 5

kΩ-

to-10

0kΩ to ensure stable operation. VOUT1, VOUT2,

VOUT3 and VOUT4 are the voltages at different VID

codes,

arranged

from

low

to

high.

Then

determine R2A, R2B and R2C as follows:

REF

1

OUT1

OUT

REF

2

V

R2A

R1

V

V

V



 



(14)

1

OUT2

OUT2

REF

2

REF

1

R2B

V

V

V

11

V

R1 R2A



 





(15)

1

OUT3

OUT3

REF

2

REF

1

R2C

V

V

V

11

V

R1 R2A



 





(16)

VOUT4 can be calculated as:

REF

1

OUT 4

OUT 4

2

V

(R1 R2A // R2B // R2C)

VV

R2A // R2B // R2C





 

(17)

Where

OUT x

V



is the output ripple determined by

equation 30.

Setting the Output Voltage-Small ESR Caps

R1

R2

Ceramic

SW

FB

Vo

L

R9

R4

C4

Figure 10: Simplified Ceramic Capacitor Circuit

When using a low-ESR ceramic capacitor on the

output, add an external voltage ramp to FB

through resistor R4 and capacitor C4. The ramp

voltage, VRAMP, influences the output voltage

besides the resistor divider shown in Figure 10.

Equation 7 calculates VRAMP.

Choose R1 within 5

kΩ-to-100kΩ. The value of

R2 then is determined as follows:

)

V

(V

)

R9

R4

1

R1

1

(

V

R2A

FB(AVG)

OUT1

FB(AVG)











(18)

R2A

1

R9

R4

1

R1

1

V

V

V

1

R2B

FB(AVG)

FB(AVG)

OUT2













)

(

(19)

R2A

1

R9

R4

1

R1

1

V

V

V

1

R2C

FB(AVG)

FB(AVG)

OUT3













)

(

(20)

And VOUT4 also can be calculated with equation

17.

The VFB(AVG) is the average value on FB. VFB(AVG)

varies with the VIN, VO, and load condition; its

value in skip mode is lower than in PWM mode,

which means the load regulation is strictly related

to the VFB(AVG). Also the line regulation is related

to the VFB(AVG); use a lower VRAMP that meets the

conditions of equation 10 for better load or line

regulation.

For PWM operation, estimate VFB(AVG) from the

following equation:

R9

R1//R2

R1//R2

V

2

1

V

V

RAMP

REF

FB(AVG)









(21)

Usu

ally, R9 is set to 0Ω, and it can also be set

following equation 22 for better noise immunity.

Set the value to <(1/5)×R1//R2 to minimize its

influence on VRAMP.

SW

2f

C4

2

1

R9









(22)

Using equations 18 through 20 to calculate the

output voltage can be complicated. Furthermore,

as VRAMP changes due to changes in VOUT and VIN,

VFB also varies. To improve the output voltage

accuracy and simplify the R2A, R2B and R2C

calculations, add a DC-blocking capacitor (CDC)

to filter the DC influence from R4 and R9. Figure

11 shows a simplified circuit with external ramp

compensation and a DC-blocking capacitor. The

addition of this capacitor simplifies the R2A, R2B

and R2C calculations, as per equations 23-25.