MP2733 datasheet(28/51 Pages) MPSIND

28 / 51 page

MP2733

– 4.5A SW CHARGER WITH I2C CONTROL, NVDC POWER PATH, USB OTG

MP2733 Rev. 1.1

www.MonolithicPower.com

5/18/2023

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

low transition on the SDA line while SCL is high.

A stop condition is defined as a low-to-high

transition on the SDA line while the SCL is high

(see Figure 11).

SDA

SCL

Start (S)

Stop (P)

Figure 11: Start and Stop Conditions

For data validity, the data on the SDA line must

be stable during the high period of the clock. The

high or low state of the SDA line can only change

when the clock signal on the SCL line is low (see

Figure 12). Every byte on the SDA line must be

8 bits long. The number of bytes that can be

transmitted per transfer is unrestricted. Data is

first transferred with the most significant bit

(MSB).

Data line

stable

Data valid

Change

of data

allowed

SDA

SCL

Figure 12: Bit Transfer on the I2C Bus

Each byte has to be followed by an acknowledge

(ACK) bit, which is generated by the receiver to

signal to the transmitter that the byte was

successfully received.

The ACK signal occurs when the transmitter

releases the SDA line during the acknowledge

clock pulse. This allows the receiver to pull the

SDA line low. The SDA line stays low during the

high period of the ninth clock.

If the SDA line is high during the ninth clock, this

is defined as a not acknowledge (NACK) signal.

The master can then generate either a stop

condition to abort the transfer or a repeated start

(Sr) condition to start a new transfer.

After the start condition, a slave address is sent.

This address is 7 bits long, followed by the 8th

data direction bit (R/W). A 0 indicates a

transmission (write), and a 1 indicates a request

for data (read). Figure 13 shows the address bit

arrangement.

MSB

LSB

R/W

Slave Address

Figure 13: 7-Bit Address

Figure 14, Figure 15, Figure 16, Figure 17, and

Figure 18 show the complete data transfer

sequence.

SDA

SCL

Start or

Repeated

Start

Condition

MSB

Acknowledgement

signal from slave

ACK

Acknowledgement

signal from receiver

Stop or

Repeated

Start

Condition

Figure 14: Data Transfer on the I2C Bus

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