CSS555C datasheet(6/13 Pages) ETC

6 / 13 page

Version 1.1, May 2009

CSS555C

Micropower Timer (with Internal Timing Capacitor)

Monostable Operation

(Extended Period or “EP” Mode)

For longer time delays, the circuit in Figure 9 uses the

internal decade counter to effectively multiply the value of

the timing capacitor. Three bits in the EEPROM select a

multiplier value from 10 to 10

6. The 555 analog block is

configured as a free running oscillator, which is the input

clock to the counter. On the falling edge of TRIGGER, the

555 oscillator is enabled, OUTPUT is set high, the decade

counter is enabled and a new timing cycle begins. The

timing cycle ends when the counter reaches the selected

terminal count. Waveforms for an extended delay cycle

are shown in Figure 10.

Figure 9 – Extended Period Delay Circuit

Figure 10 – Extended Period Waveforms

In the Extended Period monostable configuration, the

duration of the timing cycle is the oscillator period

multiplied by the counter setting. The 555 oscillator is

configured for astable operation. (The internal TRIGGER

signal to the oscillator is internally tied to THRESHOLD.

See Figure 4.) VCAP oscillates between ⅓ & ⅔ VDD (or 10%

& 90% if low voltage mode is selected). The delay time

equations for both supply conditions are provided in the

following paragraph.

Extended Delay Time Equations:

For standard supply voltages (VLOW Bit = 0)

Oscillator Period (tOSC) = 0.695 x (RA+2RB) x CTotal

Total Delay Time = Counter Setting (or Mult) x tOSC

Total Delay Time = Mult x 0.695 x (RA+2RB) x CTotal

where

CTotal = CT + CTI

CT = External timing capacitor

CTI = Internal 100pF timing capacitor

For low voltage mode (VLOW Bit = 1)

Oscillator Period (tOSC) = 2.197 x (RA+2RB) x CTotal

Total Delay Time = Counter Setting (or Mult) x tOSC

Total Delay Time = Mult x 2.197 x (RA+2RB) x CTotal

The chart in Figure 11 shows nominal delay times for

multiplier settings from 1 to 10

and resistor values

(RA+2RB) from 1K

to 10M .

(The internal timing

capacitor, CTI, equals 100pF. No external capacitor.) The

resulting delay times cover an eight-decade range!

100

1000

10000

100000

1000000

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

Delay Time (sec)

Figure 11 – Extended Period Delay Chart

The component values required for some common delay

times are listed in Table 5. For this calculation, the value of

RA and RB are equal. To keep the overall power low,

values above 1M

were selected.

Delay

Multiplier

CTotal Value

RA & RB

1 msec

100pF

2.35 M

1 sec.

100pF

4.8 M

1 min.

100K

100pF

2.9 M

1 hour

500pF

3.5 M

1 day

0.01uF

4.1 M

1 week

0.1uF

2.9 M

Table 5 – Extended Period Delay Table

Note:

CTotal = CT + CTI

CT = External timing capacitor (may be zero)

CTI = Internal 100pF timing capacitor

TRIGGER

OUTPUT

VCAP

⅔ VDD

⅓ VDD

RESET

Mult = 10

CTI = 100pF

RA+2RB = 1K

10K

100K

10M

Green:

Low VDD

Blue:

Std. VDD

VDD

Trigger

Output

Reset

VDD

Dischg

Thresh

Control

CSS555C

VSS

Trigger

Output

Reset

Trigger

Output

Reset

VTH

Optional

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