CSS555C datasheet(5/13 Pages) ETC

5 / 13 page

Version 1.1, May 2009

CSS555C

Micropower Timer (with Internal Timing Capacitor)

Pin Descriptions

Pin Number

Pin Name

Primary Function (Normal Mode)

Secondary Function (EE Programming)

VSS

Ground

TRIGGER

Initiates timing cycles (Active low)

Serial Clock

OUTPUT

Timer Output (CMOS Levels)

Serial Data Out

RESET

Asynchronous timer reset (Active low)

Serial Data In

CONTROL V

Upper comparator switch level

R/W enable (Active if VCTRL < 0.5V)

THRESHOLD

Upper comparator analog input

DISCHARGE

Open drain FET, on when OUTPUT = 1

VDD

Positive voltage supply

Table 4

Applications Information

General

The CSS555C IC may be used in many applications as a

direct replacement for the popular 555 timer. It features

the lowest 555 operating current and a minimum supply

voltage of 1.2V. It also features a programmable decade

counter for generating long time delays.

An internal

EEPROM stores the counter configuration: Divide by 1

(standard 555) or divide by 10, 100, 10

3, 104, 105 or 106.

The internal counter allows long time delays to be

generated with small value capacitors.

Monostable Operation

(Standard 555 Mode)

The circuit in Figure 6 shows a monostable or “one shot”

configuration. A single, positive output pulse is generated

on the falling edge of the TRIGGER input.

When

TRIGGER goes low, a flip-flop is set, the OUTPUT pin is

set high and DISCHARGE allows the timing capacitor to

charge towards VDD via RA. When VTH reaches the upper

comparator trip level, the flip-flop is reset, OUTPUT is

forced low and DISCHARGE pulls VTH to GND. After VTH

has discharged, the circuit is ready for the next trigger

pulse. Typical signal waveforms are shown in Figure 7.

The RESET input must be held high (inactive) during the

timing cycle. If RESET is brought low, the OUTPUT pin is

immediately forced low and the cycle is terminated.

Figure 6 – Monostable Circuit (Std. Mode)

In the monostable configuration, the duration of the timing

cycle is simply the time required to charge the timing

capacitor from GND to the upper comparator trip level. The

trip level is nominally ⅔ VDD. At low supply voltages it is

increased to 0.9 VDD.

(An EEPROM bit controls this

selection.) The delay time equations for both conditions

are provided in the following paragraph.

Delay Time Equations:

For standard supply voltages (VLOW Bit = 0)

Charge time (VTH = 0V to ⅔ VDD) = 1.1 x RA x CTotal

For low voltage mode (VLOW Bit = 1)

Charge time (VTH = 0V to 0.9 VDD) = 2.3 x RA x CTotal

where CTotal = (CInternal + CExternal) or (CTI + CT)

Figure 7 – Monostable Waveforms (Std. Mode)

Figure 8 provides a log-log selection chart. It shows the

time delay for various combinations of RA and CTotal. With

the counter bypassed (Mult = 1), time delays from 1usec to

1 second are easily generated with capacitor values from

100pF to 1uF. For long time delays (or medium delay

times using small capacitor values) the “Extended Period”

configuration should be used. (See the next section.)

0.0001

0.0010

0.0100

0.1000

1.0000

0.01

0.10

1.00

10.00

100.00

1000.00

Delay Time (ms)

Figure 8 – Time Delay Chart

RA = 1K

10K

100K

Green:

Low VDD

Blue:

Std. VDD

10M

VDD

Trigger

Output

Reset

VDD

Dischg

Thresh

Control

CSS555C

VSS

Trigger

Output

Reset

Trigger

Output

Reset

VTH

Optional

TRIGGER

OUTPUT

VCAP

⅔ VDD

RESET

Mult = 1

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