M41T62 datasheet(12/40 Pages) STMICROELECTRONICS

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Operation

M41T62/63/64/65

12/40

Operation

The M41T6x clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 16 Bytes

contained in the device can then be accessed sequentially in the following order:

●

1st Byte: tenths/hundredths of a second register

●

2nd Byte: seconds register

●

3rd Byte: minutes register

●

4th Byte: hours register

●

5th Byte: square wave/day register

●

6th Byte: date register

●

7th Byte: century/month register

●

8th Byte: year register

●

9th Byte: calibration register

●

10th Byte: watchdog register

●

11th - 15th Bytes: alarm registers

●

16th Byte: flags register

2.1

2-wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a bi-

directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be

connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

●

Data transfer may be initiated only when the bus is not busy.

●

During data transfer, the data line must remain stable whenever the clock line is High.

●

Changes in the data line, while the clock line is High, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

2.1.1

Bus not busy

Both data and clock lines remain High.

2.1.2

Start data transfer

A change in the state of the data line, from high to Low, while the clock is High, defines the

START condition.

2.1.3

Stop data transfer

A change in the state of the data line, from Low to High, while the clock is High, defines the

STOP condition.

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