VV6501 datasheet(11/60 Pages) STMICROELECTRONICS

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VV6501

Functional Description

3.1.4

Digital data bus: D[4:0]

Sensor data may be either 8 or 10 bits per pixel and is transmitted as follows:

10-bit data: A pair of 5-bit nibbles, most significant nibble first, on 5 wires.

8-bit data: A pair of 4-bit nibbles, most significant nibble first, on 4 wires.

In 5-wire mode, the embedded control codes occupy only the most significant 8-bits, the least

significant 2-bits are always zero.

Output tri-state using SIF

Output pad drive strength

The data and QCK output pads are tri-stateable with 4 mA drive.

3.1.5

Data qualification clock (QCK)

A data qualification clock (QCK) is available and complements the embedded control sequences.

This clock runs continuously when enabled and consists of:

Fast QCK: the falling edge of the clock qualifies every 5 or 4-bit data blocks that constitute a

pixel value.

Slow QCK: the rising edge qualifies 1st, 3rd, 5th, etc. blocks of data that constitute a pixel

value while the falling edge qualifies the 2nd, 4th, 6th etc. blocks of data. For example in 4-wire

mode, the rising edge of the clock qualifies the most significant nibbles while the falling edge of

the clock qualifies the least significant nibbles.

Figure 6: Digital data output modes

Figure 7: QCK modes

D7,D6,D5,D4

D3,D2,D1,D0

D7,D6,D5,D4

10-bit pixel data

D9,D8,D7,D6,D5

D4,D3,D2,D1,D0

D9,D8,D7,D6,D5

8-bit pixel data

5-wire output mode

4-wire output mode

QCK (slow)

QCK (fast)

D[4:0]

<MSB>

<LSB>

<MSB>

<LSB>

<MSB>

<LSB>

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