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BTD21520 bảng dữ liệu(PDF) 9 Page - BASIC SEMICONDUCTOR

tên linh kiện BTD21520
Giải thích chi tiết về linh kiện  Dual-Channel Isolated Gate Driver
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BTD21520 bảng dữ liệu(HTML) 9 Page - BASIC SEMICONDUCTOR

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Rev.0.0
Dual-ChannelIsolatedGateDriver
BTD21520x
8.ParameterTesting
8.1PropagationDelayandPulseWidthDistortion
The figure below shows the characterization of pulse width distortion (tPWD) and delay matching (tDM).During the test, the
two inputs are synchronized while the DT pin is connected to the VCC to disable the dead time.
Figure1.DeadTimeDisabled,IN1andIN2withsynchronizedsignal
8.2RiseTimeandFallTime
Figure2.DefinitionofRiseTimeandFallTime
8.3 InputandDisableResponseTime
When the DIS pin is connected to the controller at a certain distance, it is recommended to configure a bypass capacitor
of about 1nF with low stray inductance close to the DIS pin.
Figure3.DisablePinTiming
8.4ProgrammableDeadTime
DT pin left open or connected to GND via resistor RDT sets dead time between two channels.
Figure4.DeadTimeSetting
tPLH1
tPLH2
tDM
tPWD2
=
tPLH2
-tPHL2
tPHL2
tPHL1
IN1/IN2
OUT1
OUT2
tf
90%
10%
tr
20%
80%
DIS High Response Time
DIS Low Response Time
tPHL
tPLH
IN1
DIS
OUT1
OUT2
OUT1
IN2
IN1
t
tPHL
tPHL
tPLH
Dead Time
(set by RDT)
Dead Time
(Determined by Input signals
if longer than DT set by RDT)
90%
10%
90%
tON1
tON2
tDM
tPWD2
=
tON2
-tOFF2
tOFF2
tOFF1
IN1/IN2
OUT1
OUT2
tf
90%
10%
tr
20%
80%
DIS High Response Time
DIS Low Response Time
tOFF
tON
IN1
DIS
OUT1
V
t
OUT2
OUT1
IN2
IN1
V
t
tOFF
tOFF
tON
Dead Time
(set by RDT)
Dead Time
(Determined by Input signals
if longer than DT set by RDT)
tPLH1
tPLH2
tDM
tPWD2
=
tPLH2
-tPHL2
tPHL2
tPHL1
IN1/IN2
OUT1
OUT2
tf
90%
10%
tr
20%
80%
DIS High Response Time
DIS Low
Response Time
tPHL
tPLH
IN1
DIS
OUT1
OUT2
OUT1
IN2
IN1
t
tPHL
tPHL
tPLH
Dead Time
(set by RDT)
Dead Time
(Determined by Input signals
if longer than DT set by RDT)
90%
10%
90%
50%
50%
90%
10%
10%
90%
50%
50%
50%
50%
10%
tPLH1
tPLH2
tDM
tPWD2
=
tPLH2
-tPHL2
tPHL2
tPHL1
IN1/IN2
OUT1
OUT2
tf
90%
10%
tr
20%
80%
DIS High Response Time
DIS Low
Response Time
tPHL
tPLH
IN1
DIS
OUT1
OUT2
OUT1
IN2
IN1
t
tPHL
tPHL
tPLH
Dead Time
(set by RDT)
Dead Time
(Determined by Input signals
if longer than DT set by RDT)
90%
10%
90%
50%
50%
90%
10%
10%
90%
50%
50%
50%
50%
10%



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