M41T93 datasheet(29/49 Pages) STMICROELECTRONICS

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M41T93

Clock operation

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3.8.1

TI/TP

●

TI/TP = 0

IRQ/FT/OUT is active when TF is logic '1' (subject to the status of the Timer Interrupt

Enable Bit (TIE).

●

TI/TP = 1

IRQ/FT/OUT pulses active according to Table 8 (subject to the status of the TIE Bit).

Note:

If an alarm condition, watchdog time-out, oscillator failure, or OUT = 0 cause IRQ/FT/OUT to

be asserted low, then IRQ/FT/OUT will remain asserted even if TI/TP is set to '1.' When in

pulse mode (TI/TP = 1), clearing the TF Bit will not stop the pulses on IRQ/FT/OUT. The

output pulses will only stop if TE, TIE, or TI/TP are reset to '0.'

TF and IRQ/FT/OUT become active simultaneously.

n = loaded countdown timer value. The timer is stopped when n = 0.

3.8.2

At the end of a timer countdown, TF is set to logic '1.' If both timer and alarm interrupts are

required in the application, the source of the interrupt can be determined by reading the flag

bits. The timer will auto-reload and continue to count down regardless of the state of TF Bit

(or TI/TP Bit). The TF Bit is cleared by reading the Flags Register.

3.8.3

TIE

In Level mode (TI/TP = 0), when TF is asserted, the interrupt is asserted (if TIE = 1). To

clear the interrupt, the TF Bit or the TIE Bit must be reset.

3.8.4

●

TE = 0

When the Timer Register (10h) is set to ‘0,’ the timer is disabled.

●

TE = 1

The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the

counter will begin from the same value as when it was disabled.

Table 8.

Interrupt operation (Bit TI/TP = 1)

Source clock (Hz)

IRQ(1) Period(s)

n(2) = 1

n > 1

4096

1/8192

1/4096

1/128

1/64

1/60

1/64

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