ST7L19 datasheet(27/138 Pages) STMICROELECTRONICS

27 / 138 page

ST7L15, ST7L19

27/138

SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d)

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in Section 13 ELECTRICAL

CHARACTERISTICS.

7.5.3 External Power-On RESET

If the LVD is disabled by the option byte, to start up

the microcontroller correctly, the user must use an

external reset circuit to ensure that the reset signal

is held low until VDD is over the minimum level

specified for the selected fOSC frequency.

A proper reset signal for a slow rising VDD supply

can generally be provided by an external RC net-

work connected to the RESET pin.

7.5.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequences caused by the in-

ternal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET pin acts as an output that is

pulled low when VDD <VIT+ (rising edge) or

VDD <VIT- (falling edge) as shown in Figure 15.

The LVD filters spikes on VDD larger than tg(VDD) to

avoid parasitic resets.

7.5.5 Internal Watchdog RESET

The RESET sequence generated by an internal

Watchdog counter overflow is shown in Figure 15.

Starting from the Watchdog counter underflow, the

device RESET pin acts as an output that is pulled

low during at least tw(RSTL)out.

Figure 15. RESET Sequences

VDD

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

VIT+(LVD)

VIT-(LVD)

th(RSTL)in

RUN

WATCHDOG UNDERFLOW

tw(RSTL)out

RUN

RESET

SOURCE

EXTERNAL

RESET

LVD

RESET

WATCHDOG

RESET

INTERNAL RESET (256 or 4096 tCPU)

VECTOR FETCH

ACTIVE

PHASE

ACTIVE

PHASE

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