APEX20K datasheet(3/117 Pages) ALTERA

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Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

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Flexible clock management circuitry with up to four phase-locked

loops (PLLs)

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Built-in low-skew clock tree

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Up to eight global clock signals

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ClockLock® feature reducing clock delay and skew

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ClockBoost® feature providing clock multiplication and division

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ClockShiftTM programmable clock phase and delay shifting

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Powerful I/O features

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Compliant with peripheral component interconnect Special

Interest Group (PCI SIG) PCI Local Bus Specification,

Revision 2.2

for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits

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Support for high-speed external memories, including DDR

SDRAM and ZBT SRAM (ZBT is a trademark of Integrated

Device Technology, Inc.)

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Bidirectional I/O performance (tCO + tSU) up to 250 MHz

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LVDS performance up to 840 Mbits per channel

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Direct connection from I/O pins to local interconnect providing

fast tCO and tSU times for complex logic

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MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,

3.3-V, and 5.0-V devices (see Table 3)

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Programmable clamp to VCCIO

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Individual tri-state output enable control for each pin

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Programmable output slew-rate control to reduce switching

noise

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Support for advanced I/O standards, including low-voltage

differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-

series terminated logic (SSTL-3 and SSTL-2), Gunning

transceiver logic plus (GTL+), and high-speed terminated logic

(HSTL Class I)

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Pull-up on I/O pins before and during configuration

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Advanced interconnect structure

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Four-level hierarchical FastTrack® Interconnect structure

providing fast, predictable interconnect delays

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Dedicated carry chain that implements arithmetic functions such

as fast adders, counters, and comparators (automatically used by

software tools and megafunctions)

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Dedicated cascade chain that implements high-speed,

high-fan-in logic functions (automatically used by software tools

and megafunctions)

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Interleaved local interconnect allows one LE to drive 29 other

LEs through the fast local interconnect

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Advanced packaging options

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Available in a variety of packages with 144 to 1,020 pins (see

Tables 4 through 7)

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FineLine BGA® packages maximize board space efficiency

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Advanced software support

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Software design support and automatic place-and-route

provided by the Altera® Quartus® II development system for

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