APEX20K datasheet(13/117 Pages) ALTERA

13 / 117 page

Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Logic Element

The LE, the smallest unit of logic in the APEX 20K architecture, is compact

and provides efficient logic usage. Each LE contains a four-input LUT,

which is a function generator that can quickly implement any function of

four variables. In addition, each LE contains a programmable register and

carry and cascade chains. Each LE drives the local interconnect, MegaLAB

interconnect, and FastTrack Interconnect routing structures. See Figure 5.

Figure 5. APEX 20K Logic Element

Each LE’s programmable register can be configured for D, T, JK, or SR

operation. The register’s clock and clear control signals can be driven by

global signals, general-purpose I/O pins, or any internal logic. For

combinatorial functions, the register is bypassed and the output of the

LUT drives the outputs of the LE.

labclk1

labclk2

labclr1

labclr2

Carry-In

Clock &

Clock Enable

Select

Carry-Out

Look-Up

Table

(LUT)

Carry

Chain

Cascade

Chain

Cascade-In

Cascade-Out

To FastTrack Interconnect,

MegaLAB Interconnect,

or Local Interconnect

To FastTrack Interconnect,

MegaLAB Interconnect,

or Local Interconnect

Programmable

PRN

CLRN

ENA

Packed

Chip-Wide

Reset

labclkena1

labclkena2

Synchronous

Load & Clear

Logic

LAB-wide

Synchronous

Load

LAB-wide

Synchronous

Clear

Asynchronous

Clear/Preset/

Load Logic

data1

data2

data3

data4

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